SU796838A1 - Binary-to-terniary code converter - Google Patents

Description

(54) DUICHIJ CODE CONVERTER TO TRINITY CODE 1.0.1

The invention relates to computing technology, is intended to condense information through the ternary coding of numbers, and can be used to save communication links between digital blocks of a computing system. The converter is used on the transmit side of the digital blocks. A known converter of a binary code into a code 1.0, I, contains a sliding shift register with an additional bit, differentiating circuits and 1J diodes. However, this converter has low reliability and low speed, i.e. the conversion is done sequentially. Also known is a binary code converter into a ternary code 1.0D of contents of ten logic ternary elements 2. However, such a converter has a complex implementation. The closest to the proposed one is a binary code converter into a ternary code 1.0.1, containing ternary elements, the first input bus of the converter being connected to the first input of the negative signal of the first ternary element, the second input bus to the first input of the negative signal of the second ternary element and the third input bus is with the positive signal input of the second ternary element 3. This converter has a complex implementation, as it contains seven ternary logic elements. The purpose of the invention is to simplify the converter. This goal is achieved by the fact that in the binary code to triple code converter 1.0, T, which contained ternary elements, the first input converter bus being connected to the first input of the negative signals of the first threefold element, the second input bus connecting the converter to the first input of negative signals the second ternary element, and the third input bus converter is connected to the input of the positive signals of the second ternary element, the outputs of the third and fourth ternary elements are connected to the output sh In the converter, the output of the second ternary element is connected to the first and second inputs of the negative signals of the third ternary element and to the first input of the positive signals of the fourth ternary element, the output of the first ternary element is connected to the first and second inputs of the positive signals of the third ternary element and to the first input negative signals of the fourth ternary element, the first input bus of the converter is connected to the second input of the negative signals of the second ternary element and to the second the input of the positive signals of the fourth ternary element, the second input bus of the conversion. These operations form a functionally complete system of logical functions and can be implemented on the basis of ternary elements, for example, on ferrite logic elements. FIG. 1 shows a diagram of a two-step binary code converter in the ternary year 1.0, G (the first stage of the converter is elements 1 and 2, the second stage is elements 3 and 4); in fig. 2 shows a timing diagram of the converter operation.

Table 1, the reader, is connected to the second input of the negative signals of the first ternary element, the third input bus of the converter is connected to the input of the positive signals of the first ternary element and to the second input of the negative signals of the fourth ternary element. This saves three ternary logic elements. The binary code converter is made on four elements, each of which performs ternary operations, described in Table. 1. The first input bus is connected to the first negative input of the first signal, to the second negative input of the second signal and to the second positive input of the fourth elements 1, 2, 4. The second input bus is connected to the second negative input of the first and the first negative input of the second ternary elements 1, 2. The third input bus is connected to the first inputs of the positive signals of the first

and the second and second negative input signals of the fourth ternary elements 1,2,4. The output of the first element 1 is connected with the first and second inputs of the positive signals of the third and with the first input of the negative signals of the fourth ternary elements 3, 4.

On the input bus X; | - X transducer is supplied with code combinations in binary form (via bus X; | with ec2, bus Xj, -2,

natural weight

- 2)

bus X 3 at the same time on the output tires F and 2 converters

-P, (at the outputs of elements 3 and 4) code combinations in ternary form (on the F bus with a natural weight of 3 °, on the bus - 3) are drawn in / uniquely corresponding to the input signal combination. When submitting a binary code

About 1 2 3 4 5 b 7

About About About About 1 1 1 1

The operation of the converter in accordance with the input combination (000) is carried out as follows (timing diagram in FIG. 2).

The clock pulse of the first phase of the first cycle according to the logic of the element (tab 1) negative signal ro input bus X in the transducer is transmitted to the input of the negative signals of element 1, from the input bus X2 to the input of negative signals of the element 2, and from the input bus to input 1 positive element 2 signals; by a second phase pulse, a negative signal from element 1 is transmitted to the input of positive signals from element 3; the third phase pulse positive signal from the element 3 goes out of the transformation -. l, form the output combination (01) corresponding to the input combination (000).

Similarly (Fig. 1, Fig. 2 and Table 2), the transformations of the X, Xj and X bus occur. The converter 1 is represented by a positive polarity signal, and a negative polarity signal.

The clock supply system of the converter circuit {hehfazna, - this is the input code combination of signal over the bus X., - X elements 1, 2 and 4 comes through three phases (one clock cycle) of information transmission over the circuit elements (Fig. 2). The second phase pulse is read from the elements 1 and 2, the third phase is read from elements 3 and 4. The pulses are sent to the X bus; {- X 3 elements 1, 2 and 4 during the clock cycle of the nepBofl phase.

The information from the three binary bits is converted into two ternary digits according to Table. 2

table 2

1 1 about 1

about 1 1 1 I 1 about

about 1 about 1 about 1 about 1

about 1

t

the following input combinations, while the outputs P and F2 correspond to a positive polarity code 1, and a negative polarity corresponds to code G.

The use of the proposed converter. Binary code into a ternary code 1.0.1 provides, in comparison with the known simplification of the converter, an increase in the speed of the converter.

Claims (3)

. Invention Formula A binary code to ternary code converter 1.0.1 containing ternary elements, the first input bus of the converter connected to the first input of the negative signals of the first ternary element, the second input bus of the converter connected to the first input of negative sig (Nal of the second ternary element, and a third input the converter bus is connected to the input of the positive signals of the second ternary element, the outputs of the third and fourth ternary elements are connected to the output buses of the converter, differing For the sake of simplifying the converter, the output of the second ternary element is connected to the first and BTOcoiM inputs of the negative signals of the third ternary element and to the first input are positive signals of the fourth ternary element, the output of the First ternary element is connected to the first and second inputs of the third signal of the triple element and with the first input of the negative signals of the fourth third element, the first input bus of the current generator is connected to the second input of the negative signals of the second TpoHtHoro element and with the second input (Positive signals of the fourth ternary element, the second input. the converter bus is connected to the cp by the second input of the negative signals of the first ternary element, the third input bus of the converter is connected to the input of the positive signals of the first ternary element and to the second input of the negative signals of the fourth ternary element. Sources of information taken into account in the examination 1. The author's certificate of the USSR 411449, class, G 06 F 5/02, 1974. 2.Sokolov T.N. and others. Ferrite logic elements and nodes of information systems. L., LVIKA 1970, p. 186-187, fig. 4-60. 3. USSR author's certificate for application No. 2578020 / 18-24, cl. G 06 F 5/02, 1978 (prototype).