SU792572A1 - Pulse delay device - Google Patents

Description

The invention relates to a measuring technique and can be used in polar correlators for an adjustable delay of a random sequence of rectangular pulses. The known device contains a logical differentiation unit, a master oscillator, a control unit, a pulse counter, a phase-sensitive unit, a main shift register, a code comparison element and a trigger ij. The disadvantage of this device is a large amount of equipment that is caused by the use of a large-capacity basic shift register, since the number of bits the main register n is defined by the expression - where m is the maximum possible number of voltage drops of a delayed pulse sequence. The aim of the invention is to simplify the device. The goal is achieved by the fact that a pulse delay device containing a lottery differentiation unit, a master oscillator, a control unit, a pulse counter, a phase-sensitive unit, a main shift register, a reference element, codes, and a trigger are inserted three OR elements, two valves and an additional shift register, the first the synchronization input of which is connected to the output of the first OR element, the second synchronization input to the output of the second OR element, the information input to the output of the logical differentiation unit, control The main input is with the control input of the code comparison element, and the output with the counting trigger input, the second synchronization time of the main register-shift, the first input of the second OR element, and the first input of the third OR element, the output of which is connected to the input R of the pulse counter, and the second the input to the output of the logic differentiation unit and the first input of the first OR element, the second input of which is connected to the second input of the second OR element and to the output of the second valve, whose inputs are connected to the outputs of the pulse counter, controlled conductive input coupled to a fourth vyhodeti control unit.

FIG. 1 shows a block diagram of the device; in fig. 2 is a time chart illustrating the operation of the device.

The pulse delay device consists of a logical differentiation unit 1, a master oscillator 2, a control unit 3, an OR 4 element, a pulse counter 5, a phage-sensitive block 6 of a valve 7 elements OR 8 and 9 of the main shift register (ft), an additional shift register 11, the comparison code element 12 , valve 13 and trigger 14.

The device delay pulses works as follows ..

The initial state of the device is set by the control unit 3 and is explained by the time interval t in Fig. 2.

With the arrival of the signal, the recording unit 3 controls the first bit of the additional shift register 11 to one, and all other bits, zero, fixes the initial value (phase) of the input signal in the phase-sensitive block b, gives permission to count the frequency pulses with a counter and pulses 5 and. it prohibits the control inputs of the shift registers 10 and 11, and the gate 13, while the shift registers 10 and 11 shift to the right along the clock pulses supplied to their first clock inputs C1 and do not respond to the clock pulses C2 inputs.

In addition, the control unit 3 permits the passage of the signal Ua through the logical differentiation unit 1, which generates pulses at the instants of the appearance of a voltage drop in the input voltage Utt., I.e., a logical differentiation occurs. If before the impulse counter 5 overflows, the input voltage drop (section t -12Fig. 2) enters the device, then the impulse from the output of the logical differentiation unit 1 to the main register

10 shift will be recorded the contents of the counter 5 pulses, and in the additional shift register 11 - one, after which the unit 1 logical differentiation resets the counter 5 pulses

at zero and the latter starts a new pulse counting cycle, the appearance of a voltage drop does not occur, information is not recorded in register 10, and in an additional register

11, a zero is written (part t ,, -t "of Fig. 2).

Thus, the moments of transition of the pulse counter 5 to zero break the entire recorded implementation of the input signal into areas of different lengths (ty, -ti 2.j) in Fig. 2, each section has its own bit in shift register 11, and if in this area , there is a differential voltage drop (plots,, P-V of FIG. 2), a unit is recorded in the corresponding shift register register 11, if there is no differential, zero (section.). Each section in which there is a voltage drop in the input voltage corresponds to one entry in the shift register 1 °, which characterizes the distance from the beginning of the section to the differential. The minimum size of a segment is equal to the quantization step.

The recording of the delayed realization into the device is stopped either at the end of the signal recording (by the maximum duration of the realization) or by filling the main shift register 10 (the required number of input voltage drops is fixed).

Upon termination of the recording, the control unit 3 brings the device to the initial state.

When the playback signal arrives, the control unit 3, rewrites the initial value of the delayed realization from the phase-sensitive unit b to trigger 14, enables the counting of pulses by a counter of 5 pulses, issues permission to the control inputs of shift registers 10 and 11 and valve 13, while registers 10 and 11 the shift is shifted to the right only by the sync pulses fed to the inputs C2.

The code comparison element 12 sequentially compares the codes stored in the main shift register 10 with the code on the pulse counter 5, if the indicated codes coincide and if there is a unit at the output of the additional shift register 11, a pulse arrives at the count input of the trigger 14 the trigger plays an input voltage drop. After the differential is played, the signal from the output of the valve 13 produces a shift of information to the right in registers 10 and 11 and resets the counter 5 to zero, i.e. prepares the device to play the next front.

If the output of the register is 11 zero, the formation of the front at the output of the trigger 14 is not performed, the information is shifted in the register 11 due to overflow of the counter 5, in the register 10 the information is not shifted.

The introduction of an additional shift register, triple OR elements and two gates into the delay device allows to simplify the device.

Ford Formula Invention

A pulse delay device containing a logic differentiation unit, a master oscillator, a control unit, a pulse counter, a phase-sensitive unit, a main shift register, a code comparison element and a trigger whose inputs S and R are connected to the outputs of the phase-sensitive unit whose first input is connected to the first input the control unit, and the second input to the first input of the logical differentiation unit, the output of which is connected to the first synchronization input of the main shift register and to the nepBfcJM input of the control unit, The input is connected to the second output of the control unit, and the third input is connected to the output of the master oscillator, the second input of the control unit and the counting input of the pulse counter, the outputs of which are connected to the first inputs of the code comparison element and the information inputs of the main shift register, the outputs of which are connected to the second inputs of the code comparison element, characterized in that, in order to simplify the device, three OR elements, two valves and an additional shift register, are entered into it, the first synchronization input It is connected to the output of the first element OR, the second synchronization input with the output of the second element OR, the information input with the output of the logic differentiation unit, the control input with the control input of the main register, the third output of the control unit and the first input of the first valve, and the output connected to the third control input and the second input of the first valve, the tertiary input of which is connected to the output of the code comparison element, and the output to the counting trigger input, the second synchronization input of the main shift register, ne the primary input of the second OR element and the first input of the third OR element, the output of which is connected to the input R of the pulse counter, and the second input-- to the output of the logical differentiation unit and the first input of the first OR element, the second input of which is connected to the second input of the second OR element the output of the second valve, the inputs of which are connected to the outputs of the imploser counter, the control input of which is connected to the fourth output of the control unit. Sources of information taken into account in the examination. 1. Copyright certificate for the application number 2578194, cl. H 03 K 5/13, 15.02.78 (prototype).

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Claims (1)

Claim A pulse delay device comprising a logical differentiation unit, a master generator, a control unit, a pulse counter, a phase-sensitive block, a main shift register, a code comparison element and a trigger, the inputs of which S and R are connected to the outputs of the phase-sensitive block, the first input of which is connected to the first input control unit, and the second input - to the first input of the logical block differentiation ^ whose output is connected to the first input synchronized, eatsii main shift register and a first input ³ the control unit, Torah input is connected to the second output of the control unit, and a third input connected to the output of the master oscillator. the second input of the control unit and the counting input of the pulse counter, the outputs of which are connected to the first inputs of the code comparison element and to the information inputs of the main shift register, the outputs of which are connected to 15 second inputs of the code comparison element, characterized in that, in order to simplify the device, it three OR elements, two gates and an additional shift register of 20 ha were introduced, the first synchronization input of which is connected to the output of the first OR element, the second synchronization input with the output of the second OR element, information the input is with the output of the logical differentiation unit, the control input is with the control input of the main register, with the third output of the control unit and the first input of the first valve, and the output is connected to the third input of the control unit and the second input of the first valve, the third input of which is connected with the output of the code comparison element, and the output with the counting input of the trigger, the second synchronization input of the main shift register, the first input of the second OR element and the first input of the third OR element, the output of which is connected to the input R account pulses, and the second input to the output of the logical differentiation block and the first input of the first OR element, the second input of which is connected to the second input of the second OR element and to the output of the second valve, the inputs of which are connected to the outputs of the pulse counter, the control input of which is connected to the fourth output control unit.