SU786008A1 - Counter testing divider - Google Patents

Description

(54) DEVICE FOR CONTROLLING COUNTERS

BACKGROUND OF THE INVENTION The invention relates to reference measurement technology. Devices are known for monitoring the counters l, 2, containing control blocks, healers, and pulse generators. These devices, which implement various principles of circuit control, are set up to detect the fault-free fault classes. They do not provide a solution to faults beyond these classes. The closest in technical terms to the invention is a device for controlling counters 3, containing the first decoder and the after-discharge connected generator of pulses and the element I, whose OUTPUT is connected to the information output of the device, the Start input connected to the inputs Reset of the counter and the signal conditioner Malfunction and the first input of the OR element, the puff of which is connected to the Reset device output, the informational inputs of which are connected to the corresponding inputs of the second decryptor. The drawback of the device is the limited control capabilities due to the lack of verification of resetting the counters to the initial state. The aim of the invention is to increase the completeness of the control. This goal is achieved by the fact that the proposed device contains a delay element, the first and second keys, as well as a code comparison unit whose output is connected to the second input of the OR element through a delay element with the signal input of the first key and the information input of the counter whose outputs are connected to the corresponding inputs of the first decipheror and the corresponding first information inputs of the code comparison block, the second information inputs of which are respectively connected to the information inputs of the device, signal th entrance

which is connected to the signal input of the second key and the first control input of the signal conditioner Fault. The outputs of the first and second decks 4 are connected to the control inputs of the second and first keys, respectively. The output of the first key is connected to the second, and the output of the second key is connected to the third control inputs of the signal conditioner Fault, the fourth control input of which is connected to the overflow output of the counter, and the output to the control input of the element I.

The structural scheme of the proposed device is shown in the drawing, Hz denotes a pulse generator 1, the element And 2; controlled counter 3, block of comparison of codes 4, counter 5, first and second decoders 6 and 7, element OR 8, delay element 9, first and second keys 10 and 11, signal conditioner Fault 12.

The signal llycK sets the counter 5 driver 12 and the element OR 8 controlled counter 4 to the state O. At this, the signal of the driver 12 opens the element AND 2, and the pulses from the generator 1 arrive at the code of the controlled counter 3. After the first pulse enters the counter 3 block 4, forming a pulse each time, if the number recorded in counter 3 becomes greater than the number recorded in counter 5, gives a pulse. This pulse sets to O of the counter 3, and after passing through the delay element O is fed to the input of counter 5 and to the input of the key 10. If the pulse coming from block 4 has the counter 3 set to O, the decoder 7 generates a signal prohibiting the passage of a pulse through the key 1O. At the input of the imaging unit 12, the fault signal is not received. If the impulse to install in O, the counter 3 was not set to O, then the decoder 7 will not issue a blocking signal to the key 10, which will generate a pulse, which the former 12 will prevent pulses from the generator 1 to the counter 3, will give a fault signal and will display the counter 5 (first) by which the malfunction signal was issued.

If after the first operation the malfunction signal was not issued, then the counter 3 receives a packet of two pulses.

COB, after which block 4 gives a pulse, since in the counter 3 there are 1 2 pulses recorded, and in counter 5 it is one, then the counter 3 is reset and record 1 is counter 3. If this operation has not been formed a malfunction signal, then a packet of three pulses is written to counter 3

etc.

When a packet of pulses is recorded in the counter (where n is the capacity of the controlled counter), then n -1 pulses should be recorded in counter 5. In this case, the decoder 6 generates a signal prohibiting the passage of a pulse from the output of counter 3 through the key 11. In the event that the output of counter 3 appears impulse in the absence of a prohibitive signal at the output of the decoder 6, this pulse passes through the key 11 and generates a fault signal . The pulse that occurs at the output of the counter 3 after it is filled generates a signal. The end of the measurement, which is fed to the driver 12.

The invention provides the ability to check the reset of counters from any state, which expands the list of detected faults and improves the completeness of control.

Claims (3)

1. The patent of Germany No. 2621921, cl. H 03 K 21/34, published 1977. 2. USSR author's certificate number 397912, cl. q 06 R 11 / OO, 1969. 3. USSR author's certificate No. 518774, cl. Q 06 F 11/10, 1978. (prototype).