RU2007732C1 - Device for frequency check - Google Patents

Abstract

FIELD: instruments. SUBSTANCE: device has NOT gates 1 and 10, NAND gates 2 and 4, pulse generators 3 and 11, surge injector 5, reverse pulse counter 6, decoder 7 and two AND gates 8 and 9. EFFECT: simplified design. 1 dwg

Description

 The invention relates to measuring equipment and can be used in information-measuring systems to control the parameters of objects of technology.

 Known devices for frequency control.

 Their disadvantages are that they operate at fixed frequencies and their great complexity.

 Closest to the technical nature of the invention is a device for comparing frequencies, containing two shapers, a shift register, four AND elements and two OR elements.

 The disadvantage of this device is that it controls the change in a fixed frequency, which is four times less than the reference frequency, as well as low speed.

 The purpose of the invention is the expansion of the range of controlled frequencies and increase the speed of the device.

 This is achieved by the fact that in the device for frequency control, containing two formers and two elements And, introduced a reversible counter, decoder, two elements NOT, two elements AND NOT and a generator.

 The drawing shows a structural electrical diagram of the proposed device.

 The device consists of the first element NOT 1, the input of which is connected to the input of the device, the first input of the first element AND 2 and the input of the first pulse shaper 3, and the output with the first input of the second element NAND 4, the pulse generator 5, the output of which is connected to the second inputs of the first and second elements AND NOT, the outputs of which are connected to the summing and subtracting inputs of a reversible counter 6 pulses, respectively. The outputs of the latter are connected to the inputs of the decoder 7, the first two outputs of which are connected to the first and second inputs of the first element And 8, and the last two outputs - to the first and second inputs of the second element And 9, the third input of the first element And 8 through the second element NOT 10 connected with the output of the high order of the counter 6 pulses, which is connected to the third input of the second element And 9. The fourth inputs of the first 8 and second 9 elements And are connected to the output of the first driver 3 pulses and the input of the second driver 11 pulses, the output of which is connected nen with R-input of the pulse counter 6. The signal from the output of the first element And 8 indicates an increase in frequency. The signal from the output of the second element And 9 indicates a decrease in frequency.

 The device operates as follows.

 The input device receives pulses with a duty cycle equal to two. During the unit part of the period, the log level. "1" allows the passage of pulses from the generator 5 clock pulses through the first element AND-NOT 2 to the summing input of the counter. During the zero part of the period, the log level. "0" prohibits the passage of pulses through the element AND-NOT 2, passing through the inverter, allows the passage of pulses through the element AND-NOT 4 to the subtracting input of the counter 6 pulses.

 Due to the lack of synchronization and discreteness of the count, by the time the next period begins, the counter 6 can be on condition that the frequency remains unchanged in the following states: all counter outputs are in the zero state; the lowest output is in a single state, the rest is in zero; all outputs are in a single state; the junior output is in the zero state, the rest is in the single state.

 In accordance with this level log. "0" will be on the following outputs of the decoder: on the first output; at the second exit; at the last exit; on the penultimate exit.

 At the beginning of the next period, by the difference from "0" to "1", the pulse shaper 3 generates a short single pulse, which is fed to the fourth inputs of the elements And 8 and 9. But it does not pass to the inputs of the device, since the element And for the first and second cases 8 closed level log. "0" from the first or second output of the decoder 7, and the element And 9-level log. "0" from the last output of counter 6. For the third and fourth cases, the And 9 element is closed by the log level. "0" from the last or penultimate output of the decoder 7, and the And 8 element is closed by the log level. "0" from the output of the inverter 10, the input of which receives the level log. "1" from the last output of counter 6.

 At the end of the pulse from the pulse shaper 3 by the pulse shaper 11, a short pulse is formed, which, arriving at the R input of the counter 6, resets it. The absence of pulses at the outputs of the device indicates that the pulse frequency does not change.

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< N/2 · τ_n, где τ¹- длительность единичной части периода;
τ^o - длительность нулевой части периода;

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- максимально возможная разница длительностей частей периода при изменении частоты;
N - емкость счетчика 6;
τ_u - период следования импульсов с генератора.In the event that the frequency increase begins by the time the next period begins, a code greater than one remains in counter 6, since the unit part of the period is greater than zero, since the generator frequency and counter capacity 6 are selected from the condition that the maximum possible change in part of the period with a change in frequency

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<N / 2 · τ _n , where τ ¹ is the duration of the unit part of the period;
τ ^o - the duration of the zero part of the period;

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- the maximum possible difference in the durations of the parts of the period when the frequency changes;
N is the capacity of the counter 6;
τ _u is the pulse repetition period from the generator.

Thus, when the frequency increases, counter 6 remains the code
1 <K <N / 2 and the pulse from the shaper 3 passes through the And 8 element, since at its first two inputs there will be a log level. "1" from the decoder 7, and on the third - the level of the log. "1" from the element NOT 10, at the input of which is the level log. "0" from the last counter output. Element And 9 is closed by the log level. "0" from the last output of counter 6. When the frequency decreases, the unit part of the period is less than zero and the code remains in the counter
N / 2 <K <N - 1.

 In this case, the pulse from the shaper 5 passes through the And 9 element, since the log level will be at its first and second inputs. "1" from the decoder 7, and on the third - the level of the log. "1" from the last output of counter 6, the AND 8 element is closed by the log level. "0" from the element NOT 10, at the input of which is the level log. "1" from the last output of counter 7.

 The appearance of pulses on the second output indicates a decrease in frequency.

 The device is characterized in that the capacity of the counter 6 does not depend on the magnitude of the period of the input pulses, but only on the maximum possible magnitude of the change in the unit and zero parts of the period, which can significantly reduce hardware costs. (56) Copyright certificate of the USSR N 993144, cl. G 01 R 23/15, 1981.

Claims (1)

 A FREQUENCY CONTROL DEVICE, comprising two pulse shapers and two AND elements, characterized in that a reverse pulse counter, a decoder, two NOT elements, two AND elements and a pulse generator are introduced into it, the input of the first element NOT connected to the input of the device, the first input of the first element AND is NOT and the input of the first pulse shaper, and the output of the first element is NOT connected to the first input of the second element AND is NOT, the output of the pulse generator is connected to the second inputs of the first and second elements AND are NOT, the outputs are which are connected to the summing and subtracting inputs of the reversible pulse counter, and the outputs of the reversing pulse counter are connected to the inputs of the decoder, the first two outputs of which are connected to the first and second inputs of the first element And, and the last two outputs are connected to the first and second inputs of the second element And, the third the input of the first element And through the second element is NOT connected to the output of the senior discharge of the pulse counter, which is connected to the third input of the second element And, the fourth inputs of the first and second elements And are connected the first output of the pulse shaper and the input of the second pulse, the output of which is connected to the R-input of the pulse counter.