SU762157A1 - A-d converter - Google Patents

Description

. one

The device relates to computing technology and is designed to work as part of analog-digital information processing complexes, automatic control and regulation. Known analog-to-digital converters with pre-processing of statistical samples ¹ Bani transformation considering sobtnosheniya noise and quantization level values (O.

The specified analog-to-digital converter, has high speed and accuracy at fixed ratios of intrinsic noise and quantization level _1, but it does not allow reconfiguring the number of bits in the process of converting continuous information.

Known analog-to-digital voltage converters in the code, built in the form of a tracking system

with feedback, where voltage

feedback is summed—

2

increments on the reference weight resistors. High speed and accuracy of conversion in these devices is achieved by -. Additional comparison elements in the feedback circuit of code-to-voltage transducers, or by using multi-scale reading with a set of scales, level standards, adders, and comparing elements [2] and [33.

The closest to the invention is an analog-to-digital converter * consisting of a comparison element, keys, which allow switching weighted, binary-binary currents of a reversible binary counter that performs the function of a register and a control unit (43.

The disadvantage of this device

is low precision output

information while reducing the ratio

signal - noise at the input of the converter.

3

four

The purpose of the invention is to improve the accuracy of the output analog-go digital converter.

This goal is achieved in that an analog-digital converter ¹ receiver, containing a device for converting * including a comparison element, a key block, weighing elements, a reversible counter and a control block, is entered a block for automatic selection of the number of digits.

The introduction of the block of automatic selection of discharges allows you to track changes in the ratio of noise for

'by changing the level of quantization, with the maximum number of bits set at low noise levels or in the absence of noise, and the number of bits decreases with increasing

 noise level in the converted signal. due to zeroing η low-order bits from the total number N of the bits of the converter.

The optimally admissible possible number of η blocked bits from the total number of N bits is estimated experimentally, taking into account the intrinsic errors of the ADC.

FIG. 1 shows a functional diagram of an analog-to-digital converter; in fig. 2 - block diagram of the block to automatically select the optimal number of digits .. ADC.

The input of the analog-to-digital converter comes from a source of information, the signal y, containing the useful signal x and additive interference ^, y = x + «|.

The unit 1 is connected to the device input in series with each other, block 1 for extracting the interference signal, block 2 for generating the absolute value of the interference signal, scale unit 3 and block 4 for automatic selection of the number of digits, consisting of the former 4 ^ priz · nak optimum capacity and device 4 _g to block low-level gaps.

The Converter 5 consists of a comparison element 6, keys, and a block 7 of the weighing elements, a reversible counter 8 and a control block 9.

Comparing element 6 of block 4,

represents η summing

15

20

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DC amplifiers 10,

¹ per · one input, which through resistor 11 sends a signal | kP, or ΙμΊ from the output of the scale unit 3, and the other input also through resistor 11 is fed a reference voltage and _e or _e corresponding to the quantization levels 4 ₂ , ..., ς _η , when switching the corresponding discharge

10 dov reversing counter ADC. The output of each of the η amplifiers 10. element of the comparison of signals and C, is connected to the corresponding input of the switch and the shaper of the sign of the optimal width, built in the form of two groups of Schmidt triggers 12 and 13 with pairwise combined. inputs and b correspondingly configured thresholds.

. The outputs of both groups of Schmidt triggers 12 and 13 are connected directly and through the sum of the inverter NOT 14 to the inputs of the corresponding AND 15 matching elements, the signals 25 at the outputs of which indicate the optimal bit depth.

The device 42 to block the low-order bits of the ADC consists of a group of logical elements OR 16,

30 NOT pulse-potential elements of the C 18, a group of pulse amplifiers 19.. '

As shown in FIG. 2, n inputs of the block 42 are connected to the output buses of the block 4 ₁ , in which the signal of the sign of the optimum capacity is generated.

Blocking transfers from low-order bits to high-order ones occurs when the corresponding number of low-order bits are turned off and extinguished, depending on the ratio of the noise level and the threshold voltages kc and and _e .

The device 5 conversion is an electronic tracking system with feedback, working out the increment of the input value and using as re- * '

⁵⁰ gistra reversive counter 8, consisting of triggers 20, elements of the match And 21.

To control the transfer and blocking of low-order bits on the signals of 55 lam of the device 4 ₂ for blocking, the control unit 9 is used, which consists of a generator of 22 pulses, pulsed-potential

35

40

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elements And 23, one-shot 24, the element OR 25.

In order to control the transfer of the reversible counter 8, a pulse potential element 21 5 · is used.

matches It provides blocking of transfer from switchable discharges when they are zeroed for the remaining working discharges of the reversible counter 8.

The principle of operation of the proposed analog-digital converter with automatic selection of the optimal number of digits is as follows.

From the input signal y *, after transforming it in block 1, to extract 15 the interference signal in the imager 2, the absolute value of the interference signal and in the scale unit 3 a signal is generated that is proportional to the interference level

/ M | or kg) ^g | . 20

The comparison element, the switch and the shaper 4 of the sign of the optimal row width produce at the output the excitation of one of the η tires depending on the signal level received from block 3 and comparing it with the threshold reference voltages C, ...

/ Ai ·

If the signal from block 3 is less and _E1 , then none of the buses at the output of block 4 is excited, and the ADC works - ³⁰ melts with the maximum number of digits.

When the signal from block 3 reaches a certain threshold, the corresponding bus is turned on at the output of block 4 ,. The excitation of one of the 35 tires of block 4, controls the operation of block 4 _g . Unit 4 ₂ performs, depending on the excited bus, blocking and resetting the corresponding number of low-order bits of the device. 40

The number of blocked low-order bits will vary, increasing as the level of interference increases and decreasing to zero as the level of interference decreases and the stationary nature of the input signal y.

In the first case, for a signal y in a straight line, device 5 operates with a reduced number of digits and a digital code is formed at the output of the ADC

y = x + d7 + dL,

where l ¹ / is the residual part of the additive noise of the converted input signal;

- own error of the device with η blocking digits.

Due to the filtering properties of the dead zone of the device and the exclusion of the accumulated error in each treatment due to zeroing the low-order bits when they are blocked (f / the ratio + Δλ / η should be expressed.

If th *) + δΑ //,

then the number of blocked discharges η is unacceptably large and η must be reduced in order to reduce the converter’s own error & к,

In the second case, when there is no interference, either it is less than the minimum threshold level and _e1 (c) at the output. ADC get the code: y = x + l ^, where Δ / 1 <own error

converter (mouth -

• roystva 5) with the maximum possible number of digits Ν.

Analog-digital simulation of the proposed device has confirmed the increase in the accuracy of the output information of the ADC by eliminating the accumulated errors.

Claims (1)

Claim An analog-to-digital converter containing a series-connected block for extracting an interference signal, a block for generating the absolute value of the interference signal, a scale unit, a key block of weighing elements, a series-connected comparison element and a control unit, a reversible counter including N flip-flops (Ν- 1) the first and second elements of the match, and the block for extracting the interference signal is connected to the input of the comparing element and the key block, characterized in that, in order to improve the accuracy of the output This information is an ADC, a block is entered in it to automatically select the optimal number of ADC digits, including N serial connections from the reference voltage element, summing amplifier, first trigger, first inverter, third coincidence circuit, N group of elements OR, second inverter, N first and (Ν-1) second pulse-potential elec-. cops of coincidence, N amplifiers, and the second input of the summing amplifier is connected to the output of the scale unit, the input of the second trigger .. 762157 Schmidt is connected to the output of the corresponding summing amplifier, and the output with the second input of the corresponding third element is the same. Denia output of the third element ₅ falling sov- connected s.sootvetstvuyuschim input of the first element group OR ⁷ and the corresponding input of each from N to (Y-D) -th group of elements OR, the output of the first group of elements OR OR is connected to the input of the first impulse-potential element coincident. , with the first input of the corresponding first and second elements of coincidence and zero inputs of the Νth 15th group of elements OR via the second inverter, the output of the Νth group of the OR elements is connected to the first input of the corresponding first and second elements of the match, the second inputs 20 of the first and second pulsed -potential elements of coincidence are connected to the counting output of the control unit, the outputs of the first pulse-potential elements of coincidence 25 are connected to the counting input of the corresponding League · 4 The corresponding trigger of the output of the second pulse-potential elements coincides with the zero input of the corresponding trigger, the input Ν-γο of the amplifier is connected to the output Ν-γο of the second .pulse-potential element, and the output - with the output (Ν-1). of the second impulse-potential-element , the second input of the first coincidence element is connected to the subtraction output of the control unit, the second input of the second coincidence element is connected to the addition output of the control unit.