SU760111A1 - Device for computing functions of type : y=sinx - Google Patents

Description

The invention relates to the field of computer technology and can be used both as an autonomous transducer and as a peripheral device of unialized and universal digital computers operating with high-capacity words.

There are known processors for calculating the elementary functions of a table type based on read-only memory (ROM), which, in addition to ROM, includes-, the argument register, which is the register of the number of ROM. Such devices are extremely fast, high speed, but when working with words longer than 16–20 binary digits, the volume of the memory becomes, as a rule, inadmissibly large [1]. ·

The closest in technical essence and the achieved result is a device containing (argument register, block of modifications of the art-25 argument, memory blocks, multiplier block, result register, first adder and control unit, the input of the argument register is the input of the device, and the outputs of the argument register -thirty

2

This is connected to the inputs of the modification block of the argument [2].

The known device is designed to 'work' with arguments, the length of which does not exceed 1520 binary digits. A further increase in the bitness of the argument, i.e. increasing the accuracy of calculations leads to a rapid increase in hardware costs, even at modern times. At the level of development of the elemental base, it turns out to be unrealistic to work with words 50 to 60 bits long.

Thus, a disadvantage of the known device is the low accuracy of the calculation.

The aim of the invention is to improve the accuracy of calculations.

This goal is achieved in that the device containing the argument register, the argument modification block, memory blocks, the block (multipliers, the result register, the first adder and the control block, the input of the argument register being the input of the device. And the outputs of the <argument connected to the inputs of the argument modification block, a second adder, a key, a selector-mulz 760111 4 are additionally introduced

Tiplexer, zero decoders and intermediate result register, with the first group of outputs of the argument modification block connected to the inputs of the second adder, inputs of the first zero decoder and the first group of key inputs, outputs of the second output block of the argument modifications block и to the first and second blocks memory and the inputs of the second zero decoder, and the third group of outputs of the argument modification block is' θ with the inputs of the third zero decoder and the first group of inputs of the multiplexer selector, the outputs of the second adder co are connected to the second group of key inputs, the control input of which is connected to the first output of the control unit, and the outputs to the inputs of the third memory block whose outputs are connected to the second group of inputs of the selector-multiplexer, the third 20 and fourth groups of inputs of which are connected respectively to the outputs of the first and second 'memory blocks, · the control input of the selector-multiplexer is connected to the second output of the control unit, and the first and second Outputs - to the corresponding inputs'

multiplier block, the third input is connected to the first output of the intermediate result register, and the first, second and third outputs of the block are ³⁰

nozhiteley - register with the first result input, the intermediate result register and the third output respectively the eligible unit, a control unit connected to the control unit ³³ vho- house argument modification, the fourth - to the control inputs of the first, second and third decoders zero, the outputs of which are connected to a second , the third and fourth inputs of the control unit, respectively, the fifth output of the control unit is connected to the second input of the result register, the first output of which is connected to the first input of the first adder, ne vy 45 whose output is connected to the second input of the intermediate result register, the second output of which is connected sovtorym input of the first adder, a second output connected to zd

the third input of the result register and the second output of the result register is the output of the device.

The drawing shows a block diagram of the proposed device. - 55

It contains a register of 1 argument, block 2 modifications of the argument, adder 3, key 4, blocks 5 and 6 of memory, forming block 7 functional tables), selector-multiplexer 8, block 9 multipliers, register 10 result-60 theta, adder 11, register 12 intermediate result, the decoders 13 zero, forming in the aggregate the block 14 and the block 15 of the control. Block 9 multipliers, result register 10, 65

the adder 11 and the intermediate result register 12 form the operating device 16.

The proposed device implements a segmentation method, which consists in zeroing the bits located to the left of the left border of any group of bits of the argument (segment) and to the right of the right border of the segment. The most appropriate division of the argument into three segments. In this case, the formula for calculating, 51ts 4 _x looks like this:

5 <P ₂ X - = 5 <C (x + _h * _e * + $ | ^{= 5} 'P £ ^ .S09 "X ₂ SO5 GX _e -

_x 'to me. ίΐ

+ СО5 ^ Х ₁ СО5-Х ₂ -5.П ₅ Х _э =

/ Ιϊ 'ίϊ Ίί ίΐ \ 5? '

= \ 5 ₍ П-Х ₄ СО5-Х ₂₊ СО5 -Х ₁₅ П12 ^X 2) сО5 2 ^Х 3 +

x ₂ ) ₅ 1n ~ x _e .

In this case, "5 blrke stored values 5ΐηBh subfunction and in two blocks of 6 values subfunctions! N ^ x ^ x _ζ iso5 _2. The subfunctions £ x _e , cos ^ x _e are calculated

in operation block 16.

The operation of the device begins with the entry of the argument on the register of 1 argument. Then it goes to block 2 of the modification of the argument, where it is converted into’segments by signals from control block 15. The resulting segments are checked for equality to zero in block 14.

The first segment comes to the key

4 and in the adder 3, where the production of the addition of the code of the first segment is made.

Key 4 passes to the inputs of the block

5 code ~ the first segment in the case of calculating e1ts x and the addition of code when calculating 005 x.

The second segment is directly fed to the inputs of blocks 6, and the younger (third) segment to the input of the selector-multiplexer 8, at the output of which pairs of factors are formed depending on the signals from block 15.

The device 16 consists of two _multi-tap devices of the result register 10, the adder 11 and the intermediate result register 12. Each multiplying device contains the multiplier itself and the register. The first multiplier device is designed to calculate the products of pairs of subfunctions, and the second to calculate the values of the subfunctions sine and cosine of the lower segment. Register 12 is used to store intermediate results obtained in 'the process of computing functions final result formed in the register 10 results, outputs of which ^- are the outputs of the device.

760111

Calculation 81p _and £ -x and CD8 ^ x _and occurs in parallel with the computation of works other subfunctions, but operation of the second multiplier device begins earlier than the first job, as pos- 5 Jr. segment dumb device 16 immediately after the transformation argument segments through selector multiplexer A.

The operation of all blocks of the device is controlled by block 15.

Thus, at lower hardware costs, the proposed device has a calculation accuracy of 3, 6 times more than the prototype (an increase from 15 digits to 56).

Claims (1)

Claim A device for calculating functions 20 of the form «« b1пх, containing the argument register, argument modification block, memory blocks, multiplier unit, result register, first adder and control unit, the argument register-25 pa input being the device input, and the argument register outputs are connected to the inputs of the argument modification block, characterized in that, in order to increase 30 accuracy, it contains a second adder, a key, a selector-multiplexer, zero decoders and an intermediate result register, with the first group of outputs of the mod The instrumentation is connected to the inputs of the second adder, the first zero decoder and the first group of key inputs, the second group of outputs of the argument modification block — with the inputs of the first and second memory blocks and the inputs of the second zero decoder, and the third group of outputs of the argument modification block inputs third decoder zero and the first group of inputs selektoramultipleksora, outputs of second ⁴⁵ summa- torus connected with the second group vho'dov key, a control input coupled to a first / output control unit, and outputs - with WMOs s third storage unit, which outputs are 'connected to the second group of inputs of the selector-multiplexer, the third and fourth · whose input group are connected respectively to the outputs of the first and second memory blocks, the control input | The 'selector-multiplexer' is connected to the second output of the control unit, and the first and second outputs to the corresponding inputs of the multiplier block, the third input of which is connected to the first output of the intermediate result register, and the first, second-swarm and third 'outputs of the multiplier block with the first inputs of the result register ^ of the intermediate result register and the control unit, respectively, the third output of the control unit is connected to the control input of the argument modification block, the fourth to the control inputs of the first, second and third about zero decoders, the outputs of which are connected to the 'second, third; and the fourth inputs of the control unit, respectively, the fifth output of the control unit is connected to the second input of the result register, the first output of which is connected to the first input of the first adder, the first output of which is connected to the second input of the register <. intermediate result, the second _; the output of which is connected to the second input of the first adder, the second output of which is connected to the third input of the result register, and the second output of the result register is the output of the device.