SU752775A1 - Pulse train to square pulse converter - Google Patents

Description

The invention relates to a pulse technique and can be used in electronics and automation to form arc pulses whose duration is equal to the duration of a series of input pulses. A pulse is known that contains a source of input pulses of two one-oscillator, AND and OR circuits. In it, the start and reset inputs of the first one-shot, the reset input of the second one-shot and one of the inputs of the circuit I are connected to the source of input pulses; The inputs of the OR circuit are connected to the outputs of one-shot, while one of the inputs of the circuit OR is connected to another input of the circuit AND, the output of which is connected to the start input of the second one-shot. However, the -faKoe device overestimates the duration of the formed enveloping series due to the fact that after the disappearance of the series of input pulses there is one; one-shot continues to produce a pulse whose duration usually exceeds the period following the input pulses. In this case, the magnitude of the period of the succession of the input pulses is determined by the total instability of the time of the driving elements and the spreading circuits. The closest technical solution to the proposed one is a pulse train converter into a rectangular pulse containing a trigger, a pulse counter, three AND gates, a logical OR element, and three delay elements. In this case, the outputs of the mentioned delay elements are connected to the inputs of the logic elements I, the input of the first delay element is connected to a single trigger output, the input of the second delay element is connected to the single output of the high trigger trigger and to the second input of the second logic element I, the input of the third element the delay is connected to the zero output of the trigger of the most significant bit of the counter and to the second inputs of the first and third logical elements AND, the output of logical elements AND through the logical element OR are connected to the inputs reset the counter and trigger, the input of which is with the counting input of the counter and: about the device input 2.

However, in this case, the accuracy,; where the device detects a sonec of a series is equal to two periods of the input sequence.

The purpose of the invention is to improve the accuracy of the transformation.

The goal is achieved by iTO in converting a pulse sequence into a rectangular pulse containing a trigger, a single input of which is connected to the input bus, and a zero input is connected to the output of the driver, an input pulse extender, a logic element J-NOT with a free collector, a storage capacitor, a logical one. the NAND element and the inverter, wherein the input of the driver through the inverter is connected with the output of the NAND logic element, one input of which is connected to the single trigger input and zero output will expand l, and its other input is connected via a logic AND-NO element with a free outlet manifold to a single dilator input pulses and simultaneously through the storage capacitor - to the common bus.

The drawing shows a functional diagram of the proposed device.

The converter of the sequence of narrow pulses into a rectangular pulse contains a spreader of 1 input pulses, a logic element (2 AND-HEi with a free collector, a storage capacitor 3, a logical element 4 IS-NOT, an inverter 5, formatiru: pb and trigger 7, Input 8 expander 1 connected to the source of input pulses {with input bus), the zero output of the expander 1 is connected to one of the inputs of the NAND logic element and the trigger input 7. The unit expander 1 is connected via a logical NAND with a free collector 2 to the second input of the logic element 4 IS-NOT, which through the storage capacitor 3 is also connected to the common bus of the device. The output of the logical element 4 AND-NOT through a series-connected inverter 5 and driver 6 is connected to the zero input of the trigger 7, the single output 9 of which is the output of the device. In addition, the device also has an additional output 10, from which the pulse is removed. End of sequence

The converter of a sequence of narrow pulses into a rectangular pulse operates as follows.

When a supply (flowing) current is applied to it

the logic element 4 begins to charge the storage capacitor 3,

When the voltage across it reaches the threshold of the logic element 8 (approximately 1.5 V), a negative voltage drop is generated at the output of the latter, which then, after additional amplification and inversion by the inverter 5, enters as a positive differential at the input of the shaper 6. Shaper b converts it into a short negative pulse, under the influence of which trigger 7 is set to a predetermined state characterized by a logical zero (low voltage) on output 9 of the device.

The first impulse of the input sequence triggers the expander 1, which produces a 1expanded impulse, which ensures the full discharge of the charged storage capacitor 3. The storage capacitor 3 is chosen so that during the time interval between the input sequence pulses the capacitor does not have time to charge to the voltage corresponding to the threshold of the logic element 4. Capacity can be selected so that the device reacts to the disappearance of one th or more pulses of the transformed sequence,

The negative voltage drop from the zero output of the expander 1 of the trigger 7 is set to a position characterized by a logical unit at its output 9. At the same time, a high voltage level at the output 9 of the device is held for the duration of the pulse sequence. Under the influence of a positive pulse formed on the unit output of the expander 1, the output transistor of the logic element 2 is saturated and the capacitor 3, which had time to pulse to charge to a voltage slightly less than or equal to the response threshold of the logic element 4, discharges through the gap of the collector-emitter. With the arrival of each successive pulse of the sequence, the described cycle repeats. During the discharge of the capacitor 3, the logic element 4 is blocked input zannomu communication with zero output dilator 1, a zero potential with a view to avoid affecting the operation of the device destabilizing factors.

When the input pulse sequence disappears or when there are no pulses at the device input during a time interval equal to or slightly longer than the pulse following period, the voltage on the storage capacitor 3 has time to grow to the threshold level of element 4. Iodine is influenced by positive voltages on both inputs of the logic element 4, a negative voltage drop is formed at its output, which then, after additional amplification and inversion by element 5, arrives in the form of a positive voltage. differential voltage to the driver 6. The driver b converts the voltage drop into a short negative pulse acting on the output 10 of the device, under the influence of which the trigger 7 is reset

The proposed device is characterized by an increased accuracy of converting a sequence of narrow pulses into a rectangular pulse, since the moment of loss of pulses can be determined with an error of no more than the follow-up period of the input pulses.

In addition, the proposed device can be used as a pulse converter in a time interval or as an indicator of a pulse frequency deviation below a predetermined value.

Forg-5ula invention

A pulse train transducer to a rectangular pulse containing a trigger, the single input of which is connected to the input bus,. and zero — with a driver output, characterized in that, in order to increase the conversion accuracy, an INPUT pulse expander, an NAND gate with a free collector, a storage capacitor, an NAND gate and an inverter are inputted into it. the inverter is connected to the output of the logical element NAND, one input of which is connected to the single trigger input and zero output of the expander, and the other its input is connected via an NAND gate with a free collector to the single output dy dilator input pulses and simultaneously cherez.nakopitelny capacitor - to the common bus.

Information sources,

5 taken into account in the examination

1. USSR author's certificate number 406317, KL.OZK9 / 02, 1971.

2. USSR author's certificate number 577651, cl. N OZK 5/00, 1975.

Claims (1)

Claim A pulse train converter into a rectangular pulse containing a trigger, a single input of which is connected to the input bus,. and zero - with the output of the shaper, characterized in that, in order to increase the accuracy of the conversion, an input pulse generator, an NAND gate with a free collector, a storage capacitor, an NAND gate and an inverter are introduced into it, while the input the shaper through an inverter is connected to the output of an AND-NOT logic element, one input of which is connected to a single input of a trigger and the zero output of an expander, and its other input is connected via an AND-NOT logic element with a free collector to a unit output of spreader input pulses and simultaneously cherez.nakopitelny capacitor - to the common bus.