SU736367A1 - Converter of pulse burst into square pulse - Google Patents

Description

The invention relates to a pulse technique and can be used in telemechanics systems and information acquisition systems. A pulsed-to-square pulse converter is known, which contains a reference pulse generator, a counter, the outputs of which are decrypted by four coincidence circuits and two flip-flops l. Its disadvantage is low accuracy. The converter of a burst of pulses into a rectangular pulse containing an RS trigger is also known, S is the input of which is connected to the input terminal, and a single output to the output terminal, a summing counter and delay element 2. However, this converter also has a low accuracy n 5 education. The purpose of the invention is to improve the accuracy of the transform. For this purpose, the converter converts bursts of pulses into a rectangular pulse containing a K8 grigger, 5 - “the stroke of which is connected to the input terminal, and a single output to the output terminal, the summing counter and the delay Element are additionally inputted to the pulse driver, prohibition unit, and the reference generator pulses, the OR logical element and the AND logic element, and the S start of the RS flip-flop is connected to the input of the pulse former, the output of which is connected to the first input of the OR logic element and to the first input of the prohibition block, the second input of the block it is connected to a single output K S - -fggar, and the third input - to the output of the generator reference pulses, the output of the solenoid-prohibiting unit. There is a diner with a counting input of the bag {of a counting counter, and the output of a logical element OR is connected to the reset input of a summing counter, the bit outputs of which are connected to the inputs of a logical element AND whose output through an element

delays AND is connected to the R-input of the RS-flip-flop and the second input to the terminal of the IR element OR.

FIG. Figure 1 shows a structural electrical converter circuit;

in fig. 2 is a timing diagram of the operation of a pulse train converter into a rectangular pulse.

Pulse transducer converter rectangular pulse contains RS

trigger 1.5 - input, which is connected to the input terminal, and a single output to the output terminal, summing counter 2 and shaper 3 pulses, block 4 prohibition, g-generator 5 reference pulses, logic element OR 6 and logic element AND 7, and S - the input R of the 5-flip-flop 1 is connected to the input of the imaging unit 3 pulses, the output of which is connected to the first input of the logical element OR bis by the first input of the prohibition unit 4, the second input of the prohibition unit 4 is connected to the single output of the RS flip-flop 1, and the third input - with the output of the generator 5 reference pulses. The output fwioka 4 of the prohibition is connected to the counting input of the summing counter 2, and the output of the logic element OR 6 is connected to the reset input of the summing counter 2, the bit outputs of which are connected to the inputs of the logic element And 7 the output of which through the delay element 8 is connected to R - input R 5 - trigger 1 and with the second input of the logic element OR 6,

The converter works as follows;

Upon receipt of a burst of pulses at the input of the converter. FIG. 2, a). RS ..-- trsh ger i works, fixing the patch of the pack (see Fig. 2.6) and opens the prohibition block 4 with a signal from its single output. At the moment of pause, After each pulse of the packet, the pulses of the reference generator 5 pass to the counting input of summing counter 2 and are fixed by it. Each impulse of the packet arrives, except for S of the R $ -trigger chakhod, and to the input of the pulse shaper 3, which forms it in duration (see Fig. 2, c). The impulse formed by the duration from the output of the imaging unit 3 is fed to the control input of the prohibition unit 4 and closes, i descends the pulses of the reference generator 5 (see Fig. 2, d) to the counting input of the summing counter 2, simultaneously the same impulse through the logical element OR 6

resets counter 2 to the zero position. After the end of the stack, the pulses of the reference generator 5 begin to flow again to the counting input of counter 2 (see Fig. 2, d, e). If a discontinuity appears in the packet of impulses, the duration of the fixation of the fixed discontinuity, then the operation of the converter does not change. The duration of the fixed break is established by the corresponding connection of the inputs of the logic element AND 7 to the discharge outputs of counter 2 (see Fig. 2, e, g, h). The logical element And 7 decrypts the contents of counter 2 and, therefore, if the logical element And 7 operates at the position N of counter 2, then the magnitude of the fixed gap will be icpp

where Tperiod reference pulse generator.

If the size of the gap reaches or exceeds the duration of the fixed gap, then the logic element AND 7 (Fig. 2, I) and the trigger 1 and counter 2 are set to zero in pulses (see Fig. 2, k, l.). A rectangular pulse at the output of the converter ends.

Generator 5 support pulses. the pulse counter 2 and the logic element AND 7 represent the aggregate of the delay unit, which is reset to the idle state at a given time point (at the instant of the occurrence of the next pulse of the packet).

The regulation of the duration of the fixed break is carried out by connecting the inputs of the logic element AND 7 to the corresponding outputs of the account 2.

In the converter, the extension of the output rectangular Wx pulse does not depend on the magnitude of the non-fixed break in the pulse train and is always equal to Tydy NTy, and also expands the frequency range of the packet pulses, at which the burst pulse can be converted into a square pulse.

Claims (2)

1. Authors svdedelstvo USSR №362447, cl. H 03 K 5/156, 1970. 2. USSR author's certificate number 577651, cl. H 03 K 5/00, 1977 (prototype). entrance