SU729589A1 - Address shaping arrangement - Google Patents

Description

respectively, with the control output of the switch of addresses of the memory blocks and the output group of the access decoder, the inputs of which are connected to the information outputs of the switch of the addresses of the memory blocks, the first group of inputs of which is connected to the first group of inputs of the device and the second group to the output group of the priority block and a group of address outputs of the device request sources.

The drawing shows a block diagram of the device.

The device contains a block of state analysis of the requested memory blocks, a priority block 2, a switch

3addresses of memory blocks, decoder

4 references, block 5 of circulation, inputs b, 7 and 8 groups of address inputs, request inputs and inputs of the state of the memory blocks of the device, control input

9 devices, outputs 10 of the group of address outputs of the device request sources and outputs of the 11 group of address outputs of the device memory blocks. The inputs 6 to the block 1 receive the codes of the nomer blocks of the memory blocks from the sources of the requests, the inputs 7 receive the signals of the requests, and the inputs 8 to the signals of the state of the memory blocks. The input 9 to the access block 5 is supplied with a control synchronization signal for correct operation of the combinational circuit of blocks. At outputs 10 of priority block 2, response signals are issued for the information connection to the request sources backbone. On the outputs 11, address addresses are issued for starting up the operation of the corresponding memory block, as well as for information connection to the highway.

The unit 1 for analyzing the state of the requested memory blocks consists of a decoder 12 of the number of the memory block, elements AND 13 for analyzing the state of the memory, and elements OR 14 for generating the application for priority block 2. The switch 3 addresses of memory blocks consists of

. And 15 elements to pass the block address of the priority request, the OR element 16 to assemble the memory block number and issue it to the decoder 4, and the OR element 17 to block the access signal in case there are no requests.

The inversion unit 5 consists of an element MeHTOjB And 18 for outputting the circulation signals and an AND element 19 for resolving and sitaronization of the inversion signal.

The device works as follows.

Suppose that a device receives several requests to different memory blocks. If the latter are free, then all applications for connecting to the trunk will come to the priority block. Block 2 with the help of switch 3 will pass the memory block number code from the priority request for the input of the decoder 4. The latter forms the access signal, which is synchronized in the address block 5 and turns the selected memory block into operation.

Thus, the device allows to increase the reliability of her work by reducing the number of switching elements.

Claims (1)

Invention Formula A device for generating an address containing a priority block, a block of state analysis of requested memory blocks, the first group of inputs of which is a group of device address inputs, the second group of inputs is a group of device request inputs, a third group of inputs is a group of device status inputs. and the outputs are connected to the corresponding inputs of the priority block, and the reference block, the first input of which is controlling the input of the device, and the group of outputs — a group of address outputs of the memory blocks of the device, In order to reduce hardware costs, the access descrambler and the memory block address switch are entered into the device, and the control input and input group of the circulation unit are connected respectively to the control output of the switch, memory block addresses and a group of outputs of the call decoder whose inputs are connected to information outputs of the switch of addresses of memory blocks, the first group of inputs of which is connected to the group of address inputs of the device, and the second group - to the Output group of the block a and the group address output source device requests. Sources. Information taken into account in the examination 1, USSR Author's Certificate No. 552845, cl. G About F 15/16, 1976. 2, USSR Authorship Certificate  458828, cl. G 06 F 9/18, 1975 (prototype).