SU725257A2 - Device for synchronizing by cycles - Google Patents

Description

The invention relates to radio engineering and can be used in communication systems with pulse code modulation for the purpose of determining the transmission of the location of clock pulses and the further implementation of synchronization over cycles.

According to the main car .. svid. No. 565402, a cycle synchronization device is known, from the 1inserts input clock driver and N blocks of opp6by pulsed positions with expanders, as well as the distributor and serially connected elements I-ILY, OR, and the delay element whose input and outputs are connected to the corresponding inputs of the pulsing positions of the pulsed positions, and the output and input of the first expander are connected to the corresponding inputs of the element I directly and through the drive, as well as the shift register, the signal overwriting node is not according to the prohibition element, the output of the clock clock directly and, through serially connected, edemeI: prohibition T and the distributor divider are connected to the corresponding inputs of the shift register, one group of outputs of which is connected to the corresponding inputs of the pulse position testing units, the overwriting node the signals of inconsistencies and the elements AND-OR, and the other group of outputs - to the input, the first expander directly, and to the inputs (N-1) of the expanders - through the AND element, with the outputs p sshiriteley directly connected to respective vhoda1M AND-OR, the output of which is connected to the second input element of the ban, and rewriting the node yyhod

5 mismatch signals are connected to the auxiliary input of one of the expanders 1 ..

However, the known device has insufficient noise immunity, /

The purpose of the invention is to improve the noise immunity of the cycle synchronization device ..

To achieve this goal in

Claims (1)

5 a synchronization device for cycles containing a clock-pulse driver and N blocks for testing pulse positions with expanders, as well as a divider-distributor and serially connected AND-OR, OR elements and a delay element, the input and outputs of which are connected to the corresponding inputs units for testing pulse positions, with the output and input of the first expander connected to the corresponding inputs of the element AND directly through the drive, as well as the shift register, the node. and the prohibition element, when etsm output of the clock pulse generator, is directly and via successively connected elements of the prohibition and sharing the ram separator connected to the corresponding shift register inputs, the output group of which is connected to the corresponding inputs of the pulsed position testing blocks,. signals of inconsistencies and elements AND-OR, and another group of outputs - to the input of the first expander directly, and to the inputs (N-1) of the expanders - through the AND element, and the outputs of the extenders Nep directly connected to the corresponding inputs of the EL-OR loop, the output of which is connected to the second INPUT of the prohibition element, and the output of the rewriting node of the mismatch signals connected to the additional input of a single expander, sequentially connected integrator, low-pass filter, comparator and regenerator, output which is connected to the inputs N of the pulse position testing units, and the output of the clock pulse generator is connected to another input of the regenerator and the input of the integrator, the output of which is connected to th input of the comparator, at the other input FBS served integrator input signal. Fig. 1 shows a structural electrical circuit of the device; in fig. 2 - timing diagrams explaining the operation of the proposed device. The cycle synchronization device contains a shaper 1 clock pulses, blocks 2, 3 and 4 testing pulse positions, expanders 5, b and 7, divider-distributor 8, AND-OR elements 9, AND element 10, delay element 11, AND element 12, accumulator 13, shift register 14, wow 15 p; 0 siGyal record mismatch element 16 C & preta, integrator 17, low pass filter 18, comparator 19 and regenerator 20. The synchronization device for cycles works as follows. . in synchronism mode, the input CHI with noise (Fig. 2a) is fed to the integrator 17, which also receives the signal from the clock 1 pulse generator (Fig. 26), which controls the operation of the integrator 17. The capacity of the integrator 17 is charged only in the moments of time corresponding to high levels of the external input signal and the signal of the clock pulse generator 1, which follows with a duty cycle equal to two; at other times, the capacity of the integrator 17 is discharged by a low level of the sigal generator of the clock pulse 1. Next, the sawtooth pulses (Fig. 2c) are fed to the signal input of the comparator 19, and the reference voltage from the output of the low-pass filter 18, corresponding to the average input level of the integrator 17, goes to the reference input x of the parator 19, where the signal level is cut off, lying below the voltage level of the support (Fig. 2c). From the output of the comparator 19, the signal (Fig. 2d) goes to the regenerator 20, where the original form of the external signal is restored, but is clear of noise (Fig. 2e). The signal gating in the regenerator 20 is performed by a negative pulse difference from the driver 1 clock pulses. From the output of the regenerator 20, the generated signal enters the blocks 2, 3, and 4 testing pulsed positions. The effectiveness of the proposed device is to improve the noise immunity when the synchronization conditions in the synchronization device are achieved and maintained in cycles. The invention of the synchronization device on the cycles by author. evid No. 565402, which means that, in order to increase the Immunity, "sequentially connected integrator, low-pass filter, comparator and regenerator, the output of which is connected to the inputs N of test units of pulsed ELX positions, and the output of the clock pulse generator is connected to another The input of the regenerator and the. INPUT of the integrator, the output of which is connected to another input of the comparator, with this, the input signal is fed to another input of the integrator. Sources of information taken into account in the examination 1. USSR author's certificate 565402, cl. H 04 L 7/08, 1974 (prototype). i i Q 0 0 1 i i 01  II Lit i 1 -P rUJjTT. (. jy7JiJiJVKH 1i, 1 j H, i; j S M; J% nK4-rt