SU758548A1 - Device for shaping clock synchrosignal - Google Patents

Description

The invention relates to telecommunications and can be used in digital information transmission systems.

A device for generating a clock sync signal is known that contains a linear filter, a nonlinear converter, a time selection unit, and a clock sync shaper [1].

However, such a device has low noise immunity and a tendency to switch to reverse operation.

The purpose of the invention is improving noise immunity and eliminating reverse work.

This is achieved by the fact that in the device for generating a clock signal containing a series-connected linear filter, a nonlinear converter, a time selection block and a clock generator, are introduced between the additional output of the nonlinear converter and another input of the time selection block, a series-connected clock generator with phase definiteness, a detector and a time selection control unit, while the other output of the clock generator is connected to other inputs of the temporary selection control node and the detector.

In FIG. 1 shows a structural electrical diagram of the proposed device; in FIG. 2 is a timing chart explaining its operation.

The clock generating device comprises a linear filter 1, a non-linear converter 2, a time selection unit 3, a clock synchronizer 4, a phase definer 5, a detector 6 and a time selection control unit 7.

The device forming a clock synchronization operates as follows.

The signal passed through the communication line (Fig. 2a) is filtered in a linear filter 1 (Fig. 26) and after a nonlinear converter 2 (Fig. 2c), a discrete line at the clock frequency appears in its spectrum, which is allocated by the sync signal generator 5 with Phase certainty .

After the nonlinear converter 2, the pulse train passes through the time selection block 3 to the clock generator 4 and its signal (Fig. 2d) eliminates the random pulse train located in the middle of the clock intervals through the time selection control unit 7 in the time selection block 3 (figv). Due to this, a periodic 10 pulse sequence (Fig. 2e) is supplied to the input of the clock synchronizer 4, and a periodic sequence of strobe pulses located at the boundaries of the clock intervals (Fig. 2e) is generated at its second output.

If during short breaks in communication 15 the phase of the voltage (Fig. 2d) changes by about 180 °, then as a result of comparing the phases of this voltage with the voltage of the driver 5 of the clock signal with a certain phase, the voltage at the output of the detector 6 through the node 7-20 equalization by time selection will stop voltage input (Fig. 2d) to the second input of block 3 of temporary selection. Therefore, the complete pulse sequence of the nonlinear converter 2 25 (Fig. 2c) will pass through this block and the required voltage phase will be restored to the clock driver 4 (Fig. 2d), i.e. the phenomenon of reverse work is automatically eliminated.

Claims (1)

The invention relates to electrical communication in digital information transmission systems. A clock sync signaling device is known, comprising a serially connected linear filter, a non-linear converter, a time selection block and a clock sync driver 1. However, such a device has low noise immunity and a tendency to switch to reverse operation mode. The purpose of the invention is to increase noise immunity and eliminate reverse operation. This is achieved in that a clock sync signaling device containing a serially connected linear filter, a nonlinear converter, a time selection block and a clock synchro generator is inserted between the additional output of the nonlinear converter and another input of the time selection block connected in series with a phase definition, a detector and a time selection control node, with another clock driver output connected to other inputs of the time selection control node and the detector. FIG. 1 shows the structural electrical circuit of the proposed device; in fig. 2 shows time diagrams for his work. The clock synchro shaping device includes a linear filter 1, a nonlinear converter 2, a time selection block 3, a clock sync generator 4, a synchrometer shaper 5 with phase definition, a detector 6 and a time selection control unit 7. The clock synchro-shaping device operates as follows. The signal passing through the link (Fig. 2a) is filtered in the linear filter 1 (Fig. 26) and after the nonlinear converter 2 (Fig. 2b) a discrete line appears at its frequency at the clock frequency, which is formed by 5 sync signal with Phase certainty. After the nonlinear converter 2, the sequence, sequence and pulses through the block 3 time selection enters the clock clock shaper 4 and its signal (Fig. 2d) through the time selection control node 7 in the time selection block 3 eliminates a random sequence of pulses located in the middle of the clock intervals (Fig. 2c.) Due to this, a periodic sequence of pulses arrives at the input of the clock synchronizing signal generator 4 (Fig. 2e), and a periodic succession is formed at its second output strobe pulses located at the boundaries of the clock intervals (fig. 2e). If during short interruptions the phase of the voltage (fig. 2d) changes by about 180 °, then by comparing the phases of this voltage with the voltage of the clock 5 of the clock signal with the phase definition The voltage at the output of the detector 6 through the time selection control unit 7 will stop the flow of voltage (Fig. 2d) to the second input of the time selection unit 3. Therefore, a full pulse sequence of nonlinear converter 2 (Fig. 2c) will pass through this block and the required voltage phase (Fig. 2d), i.e., will be restored to the clock synchro shaper 4. the phenomenon of reverse operation is automatically eliminated. Claims A clock sync signaling device comprising a serially connected linear filter, a non-linear converter, a time selection block and a clock sync driver, characterized in that, in order to improve noise immunity and eliminate reverse operation, they are inserted between an additional output of a non-linear converter and another input of the time selection bdoka sequentially connected clock generator with phase definition, detector and control unit time 1shoy selection at ztom other output of the clock connected to the clock inputs of the other node and controlling the temporal selection detector. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 457183, cl. H 04 L 7/02, 1972 (prototype). US / but xt.zlvvl zk / M z  Well Fi.2