SU721853A1

SU721853A1 - Rapid-access storage checking device

Info

Publication number: SU721853A1
Application number: SU782668810A
Authority: SU
Inventors: Лим Флегоньевич Салямов; Игорь Кириллович Шопен; Равза Минебайновна Колясникова
Original assignee: Предприятие П/Я В-2969
Priority date: 1978-10-02
Filing date: 1978-10-02
Publication date: 1980-03-15

Description

Изобретение относится к области запоминающих устройств и может быть использовано для контроля кубов памяти, накопителей, запоминающих устройств (ЗУ) автономно и в составе цифровых вычислительных машин.The invention relates to the field of storage devices and can be used to control memory cubes, drives, storage devices (memory) autonomously and as part of digital computers.

Известно устройство для контроля оперативной памяти, содержащее, кроме обычных блоков вычислительных устройств, триггер со счетным входом, - включенный : · например, между разрядными входом и выходом ЗУ. Правильность функционирования разряда контролируется на выходе ЗУ с помощью осциллографа по характерному мельканию выходных импульсов [13. ₍ A device for controlling RAM is known, which contains, in addition to conventional blocks of computing devices, a trigger with a counting input — included: for example, between a bit input and an output of a memory device. The correct functioning of the discharge is controlled at the output of the memory using an oscilloscope by the characteristic flickering of the output pulses [13. ₍

Недостатком этого устройства являет— ся невысокая полнота контроля.The disadvantage of this device is the low completeness of control.

Наиболее близким техническим решением к данному изобретению является устройство для контроля оперативной па— . мяти, содержащее последовательно соединенный генератор тактовых импульсов и счетчики, дешифраторы, схему сравнения,, элементы И и ИЛИ, первый триггер, пр»^ чем одни из выходов первого и второго счетчиков подключены соответственно ко входам первого и второго дешифраторов, другие выходы первого и второго счетчиков и выход третьего счетчика соединены со входами элементов И, выходы которых подключены ко входам элемента ИЛИ, вход первого триггера соединен с выходом элемента ИЛИ, а выходы подключены к одним из выходов устройства, входы схемы сравнения соединены соответственно с одним из выходов первого триггера входом устройства [2].The closest technical solution to this invention is a device for monitoring operational pa—. memory containing a serially connected clock generator and counters, decoders, a comparison circuit, AND and OR elements, the first trigger, etc. ”than one of the outputs of the first and second counters are connected respectively to the inputs of the first and second decoders, the other outputs of the first and second counters and the output of the third counter are connected to the inputs of the AND elements, the outputs of which are connected to the inputs of the OR element, the input of the first trigger is connected to the output of the OR element, and the outputs are connected to one of the outputs of the device, the inputs of the circuit Avoniya connected respectively to one of the outputs of the first trigger device input [2].

Недостатком этого устройства является отсутствие проверки сохранности информации в контролируемом адресе при многократном обращении к соседним с ним адресам, что необходимо для ЗУ, элементы памяти которых имеют общую среду. Этот недостаток снижает полноту контроля памяти.The disadvantage of this device is the lack of verification of information safety in a controlled address upon repeated access to addresses adjacent to it, which is necessary for memory devices whose memory elements have a common environment. This flaw reduces the fullness of memory control.

Целью изобретения является увеличение Полноты контроля.The aim of the invention is to increase the completeness of control.

*·. 4>·* ·. 4>

153 4 шахматном порядке. От начального положения > триггера 8₂ , управляющего включением координатных ключей 10 через элементы И 2₃- 2_п+2 зависит какая из половин адресов ЗУ будет выбираться При заполнении счетчиков 1 и 1_J(задержка переключения триггера 8, по счетному входу на один такт позволяет перейти на обращение к адресам другой 'θ половины. С помонью двух многовходовых элементов И 2₍ , 2^ с выходов счетчиков 1_г , 1₃ и 1^ выделяются два состояния: первое, когда они все обнулены, и второе — когда счетчики 1₂ ¹⁵ и 1₃ заполнены, а 1^ - обнулен. После обнуления счетчиков и дальнейшего поступления тактовых импульсов в одну группу адресов записывается некоторая информация, и последняя запись будет многократно повторяться по зигзагам и циклично до заполнения счетчика 1, .153 4 staggered. From the starting position> trigger 8 ₂ , which controls the inclusion of the coordinate keys 10 through the AND 2 ₃ - 2 _{p + 2} elements, which of the half of the memory addresses will be selected when filling in the counters 1 and 1 _{J (} delay switching trigger 8, by counting input for one clock cycle allows you to go to the addresses of the other half of θ. With the help of two multi-input elements And 2 ₍ , 2 ^ from the outputs of the 1 _g , 1 ₃ and 1 ^ counters, two states are distinguished: the first when they are all reset, and the second when the counters 1 ^{on February ₁₅} and March ₁ it is filled, and 1 ^ - reset After reset counters and thereafter. Incoming clock Sheha some information is recorded in one group of addresses, and the last record is repeated as many times zigzags and cyclically to fill the counter 1.

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Схема сравнения 5 вырабатывает эталонные сигналы, аналогичные поступающим на усилители записи ЗУ 6 и включается после первого обращения ко всем адресам ЗУ 6 (на втором цикле теста). Сигналы с выходов ЗУ 6 сравниваются с эталонными.Comparison scheme 5 generates reference signals similar to those supplied to the memory amplifiers of memory 6 and turns on after the first access to all addresses of memory 6 (in the second test cycle). The signals from the outputs of the memory 6 are compared with the reference.

³⁰ Предлагаемое устройство при минимуме -электронного оборудования позволяет увеличить полноту контроля ЗУ, а следовательно, надежность готовых изделий, включающих ЗУ. Особенно эффективно уст— ³⁵ ройство для контроля ЗУ, элементы памяти которых имеют общую запоминающую среду, например ЗУ, содержащих магнитные дешифраторы на пластинах с равномерными отверстиями, работающими по принципу ⁴⁰ полувыборки со смешением. · ^{30 The} proposed device with a minimum of electronic equipment allows to increase the completeness of control of the memory, and therefore, the reliability of finished products, including memory. Especially effective Device for ³⁵ roystvo to control memory, which memory cells have a common storage medium, such as memory containing magnetic decoders on plates with uniform holes, operating on the principle of ⁴⁰ poluvyborki with mixing. ·

Claims

3 The goal is achieved by the fact that the proposed device contains the AND and OR elements, the second trigger and the NOT element, the inputs of one of the additional AND elements are connected to the outputs of the clock generator and the elements, respectively, and the output is connected to the input the second trigger, the element input is NOT connected to the output of the element OR, the inputs of additional elements OR are connected to the outputs of the second decoder, the first inputs of other additional elements AND are connected to the outputs of the second trigger, the second input - to the outputs of the additional element or, and outputs - to the core GIM output device. The drawing shows a block diagram of the proposed device. The device contains counters 1., 1 elements AND 2. and 2 ,, element OR 3 decoders 4 and 4, j, comparison circuit 5, Inputs and outputs of the device (Connected respectively to the controlled memory 6. The device also contains a clock generator 7, the first 8 and second 8 trigger, the element is NOT 9, additional elements AND 2 -2 and additional elements OR 3, where n is an integer, the coordinate bus keys 10 and recording keys 11, Element inputs. And 2, are connected respectively to the generator outputs 7 and the element is NOT 9, and the output is connected to the input of the trigger 8. The input of the element is NOT 9 Switched to the output of the element IL. The inputs of the element OR 3, - 3 ,,, are connected to the outputs of the decoder 4 2. The first inputs of the elements AND 2, j are connected to the outputs of the trigger 8, the second inputs to the outputs of the elements OR 3, and the outputs - to the outputs of the device.The device works as follows: The clock pulses of the generator 7 change the state of the counter Ig. a then - the counter 1, the 4h decoders control the switching on of the coordinate tires 10 of the memory through the elements OR 3 ,, -Z, , and, and 2 - 2. Next, there is a sequential enumeration of w X and the choice of addresses by zigzag along two adjacent coordinate pins of U. When running around all the values of the counter Ij, half of the addresses of the memory that is located relative to each other in 53 akhmatny order is selected. From the initial slopes. trigger & controlling the inclusion of the coordinate keys iO through the elements AND 2 (2 depends on which half of the addresses of the memory will be selected. When the counters 1 and 1 are filled, the delay in switching the trigger 8 through the counting input per cycle allows you to go to the addresses of the other half. With the help of two multiple-input elements "ij, two states stand out from the outputs of counters 1 2 I j. And co. One, when they are all zeroed and the second when counters 1 and Ig are filled, and 1 is zero. After zeroing the counters and further arrival of clock pulses in one group Some information is recorded in the addresses, and the last entry will be repeated several times in zigzags and cyclically until the counter 1 is full. Comparison diagram 5 generates reference signals similar to those supplied to the amplifiers (records of memory 6 and turns on after the first access to all addresses of memory 6 (in the second cycle test. The signals from the outputs of the memory 6 are compared with the reference ones. The proposed device with a minimum of electronic equipment allows to increase the completeness of the memory control, and therefore the reliability of the finished products, including memory, enno efficiently inspecting apparatus memory, elements which are obshugo zapominayushuyu medium, for example memory containing magnetic decoders on plates with uniform holes, operating on the principle poluvyborki with mixing. Claims An inventive memory control device comprising a serially connected clock generator and counters, decoders, a comparison circuit, AND and OR elements, a first trigger, one of the outputs of the first and second counters are connected to the inputs of the first and second decoders, respectively, and the other outputs the first and second counters and the output of the third counter are connected to the inputs of the AND elements, the outputs of which are connected to the inputs of the j element OR the input of the first trigger is connected to the OR output of the OR element, and you The plots are connected to one of the outputs of the device, the inputs of the comparison circuit are connected respectively to one of the outputs of the first trigger and the input of the device, characterized in that in order to increase the completeness of the control, it contains additional elements AND and OR, the second trigger and the element is NOT, and the inputs of one of the additional elements AND are connected respectively to the outputs of the clock pulse generator and the element NOT, and the output is connected to the input of the second trigger, the input of the element is NOT connected to the output of the element OR, the inputs of the additional element comrade OR connected to the outputs of the second decoder, the first inputs of other additional elements and are connected to the outputs of the second Trigg. pa, the second inputs - to the outputs of the additional elements OR, and the outputs - to the other outputs of the device. Sources of information taken into account during the examination 1. USSR author's certificate No. 341087, cl. G 11 C 29/00, 1970.

2. US patent number 378829, cl. 340-146.1, publ. 1973 (prototype).

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