SU497640A1 - Device for controlling operational drives - Google Patents

Description

one

This invention relates to memory devices.

A device for controlling operative folders is known, containing an address register connected to the decoder, a control unit connected to the read amplifiers and the control unit.

The known device conducts a single check of the controlled storage device.

Since the supply voltages, the sampling currents, the bias voltage of the threshold of the sense amplifiers are unstable and may vary randomly with time, the probability of detecting the read signals having boundary values with tolerance is less than one. Signals with limiting parameters due to all sorts of fluctuations can be perceived by the control unit either as normal or substandard.

The purpose of the invention is to increase the reliability of the device by detecting among the readable signals of the checked storage device the boundary tolerances in terms of parameters with established tolerances while minimizing the time and equipment costs.

This is achieved by including between the output of the address register and the control unit a check cycle counter containing the triggers operating in the counting mode.

The input of the test cycle counter is connected to the output of the address register, and the output to the control unit.

The drawing shows the block diagram of the device.

Device address register 1, decoder 2, checked operative drive 3, read amplifiers 4, control unit 5, control unit 6 with switch-stop circuit 7, counter 8 test cycles with triggers 9, 10 and 11, the number of which can be more than three .

The counter 8 test cycles is designed to control the multiplicity of the check of accumulator 3, the triggers 9, 10, 11 operate in IB mode counter. The counting input of the trigger 9 of the lower bit is connected to the output of the trigger 12 of the higher bit of the register 1 address, the output of the trigger 11 of the higher bit of the cycle counter is with the control unit 6.

The device works as follows.

Under the influence of control pulses of block 6, register 1 generates sequential addresses. For the checked storage device 3, the coordinate windings are selected sequentially in the worked out addresses. Read signals without distortion are amplified by amplifiers 4 readings, monitored by parameters for compliance with the established tolerances in block 5. The result of the test is to enter the switching circuit 7, in the case of a negative test result, i.e. the signal is considered substandard, the address switching stops and is carried out continuously checking at the address of the accumulator at which the non-conditioned signal was read. If the check is positive from block 5, the address switching continues. After checking the accumulator at the last address, an overflow pulse from register 1, indicating the completion of the neipBoro check cycle, is fed to the input of trigger 9 of counter 8. After the number of check cycles determined by the capacity of counter 8 is completed, the overflow pulse goes to block b to stop

control device operation

Prev Invention

A device for monitoring the operative terminals, containing an address register connected to the decryptor, a control unit connected to the read amplifiers and a control block, characterized in that, in order to increase the reliability of the device and the control accuracy, it contains a check cycle counter, the input of which is connected output register of the address, and the output - to the control unit.