SU690562A1 - Semi-permanent storage - Google Patents

Claims (2)

(54) HALF-PERMANENT STORAGE IN :: the odes of elements AND the second group are connected to the outputs of the elements NOT, the outputs of the elements AND nipseft groups are connected to the inputs of erasing INTERMETERS, the outputs of the elements and the second group are connected to the inputs of the 31PYUY drivers; Here is a block diagram of a semi-permanent blocker device. The device supports drive 1 on elements 2 with ira-destructive reading of information, for example, ionotronic field-effect transistors, address register 3, vocabulary address decoder 4, clock generator 5, buffer key group 6, write register 7, group of elements HE 8, first 9 and second 10 groups of elements And, trigger rewriting And, erasers 12 and record formers 13. If it is necessary to rewrite information in drive 1, a clock generator 5 is started, the output pulse period of which is determined by the duration l cycle of rewriting. The rewrite trigger 11 changes from one stable state to another two times during one rewriting cycle, with the time of the first transfer coinciding with the rewriting time, and the moment of the second transfer dropping it in half into half erase and half-writing. So, in the initial state, that is, at the beginning of the next rewriting cycle, in the rewrite trigger AND recorded zero, in the register of record 7 is the code to be written to Some dictionary line of drive 1, and in the register of address 3 the code corresponding to the number of this dictionary line . During the erasure half-cycle, the potential corresponds to a logical unit at the zero output of the rewriting trigger 11, so you can only get it from the first group of 9 elements I. Suppose that in the iM bit selected by the decoder of the 4 vocabulary line, one was written, and -ro trigger register of record 7 bypassing zero. In this and only in this | case, all three inputs of the i-ro element And from 1 group 9, units are received: from zero output (-HR record register trigger 7, from an inevitable rewrite trigger 11, and from i-ro storage element 1 Therefore, the output of the i-ro element of AND from group 9 also shows a unit, which, arriving at the input of the I-th eraser (12t), generates an erase pulse, as a result of which the i-th memory element of the dictionary line goes to the state of the mud In Schnqo half-erase erased trigger alias 11 is redrawn from zero to one and in the second half of the rewriting cycle, i.e. the half-cycle of recording, at the single output of the rewriting trigger 11, the potential corresponds to one, therefore the signals can appear only at the outputs of the second group of 10 elements I. Let the i-th bit be chosen decryptor 4 vocabulary lines, was written zero, and to write from the i-ro trigger register 7 it is necessary to 1. In this and only in this case, all three inputs of the i-ro element And from the group Y are units: from the single output i- ro register trigger record 7, single output and the rewriting trigger 11 and output I: 5 elements are NOT from group 8, the output of which is zero from the output of the i-ro storage element of accumulator 1. Therefore, at the output of the 1st element AND from group 10, the unit that goes to the input of the i-ro entry writer (13 ;,), causes the generation of a write pulse, with the result that the t-th storage element of the given vocabulary line changes to a state of one. Thus, if the preceding character in the storage element and the newly recorded character from the corresponding register register 7 do not match, that is, one-zero or zero-one, then the rewrite pulse will pass through this memory element only in one of two half-periods, There is, respectively, in the erasure half-period or in the half-period of the record. If the characters in question are the same, i.e. zero-zero or one-unit, then neither in the erasure half-period nor in the half-time of the recording the rewriting pulses pass through the memory element, and it does not change during the entire rewriting cycle. The erase marks and entries have the opposite polarity. The pulse duration for the output of the address decoder of the dictionary line 4 is equal to the duration of the rewrite cycle, and this pulse not only reads information from the selected vocabulary, but also opens the corresponding buffer key from group 6 through which the rewrite pulse passes in this cycle. At the end of this rewrite cycle, rewrite trigger 11 is again transferred to the ilul, and the sync pulse from the output of the clock generator 5 records inf | 0r-math code to the write register 7 and the address code to the address register 3. These codes come from external to the device being described. blocks. The half-empty memory device has returned to its original state. The half-empty memory device differs favorably from the prototype, since the service life of the accumulator increases and the storage of its storage elements is eliminated, which increases the reliability of the device. Due to the line-by-line rewriting and reading of information, the device speed is increased. The invention is a half-empty memory device containing a drive, the output of which is connected to the inputs of the elements NOT, a record register and an address register that synchronizes the inputs of which are connected to the output of the clock generator, a rewriter trigger and erasers and writers whose outputs are connected to the input tires of the drive , characterized in that, in order to increase the reliability and fast operation of the device, two groups of AND elements are introduced into it, the first inputs of the AND elements of the first group are associated with you drive busbars, second inlets of elements AND of the first group are associated with zero output of the rewriting trigger; third inputs of elements AND of the first group are associated with zero outputs of the write register, single outputs of which are connected to the first inputs of elements AND of the second group, the second inputs of which are connected to a single output of the rewriting trigger, the third inputs of the elements of the second group are connected to the outputs of the elements NOT, the outputs of the zlemeite And the first group are connected to the inputs of the erasers, the outputs of the elements of the second group - input of recording. Sources of information taken into account during the examination 1. Electronics, 1975, Vol. 48, N 17, p. 80 2. US patent N 3886532, cl. 340-173R. UTP Gz1 {B