SU662936A1 - Arithmetic operation for performing operations on several numbers - Google Patents

Description

.J, - -.......- J:. -. .v .... x.-u: -. The aim of the invention is to increase speed. In the proposed device, this is achieved by the fact that it contains a result forming unit, a shift register and an N-1 delay element, the input j-ro (, N - 1) of the delay element being connected to the input bus (j + 2) -ro rand, and the output to the first information input of the (j + l) -ro decision block for performing two numbers, the output of which is connected to the second information input of the (j + 2) -ro decision block for performing operations on two numbers and the corresponding input of the second switch group, with the output of the N-ro decision block for performing operations over two numbers are connected to the third information input of the first decision block to perform operations on two numbers, the switch output is connected to the first input of the result generation unit to the second input of which the output of the control unit is connected, the output of the code comparison block is connected to the third input, the first group of inputs which is connected to the outputs of the register of the end of the operation, the second group of inputs is connected to the corresponding outputs of the shift register and the control inputs of the decision blocks for performing operations hell two numbers, the shift register input connected to the output blo ka control .. The drawing shows a block diagram of the arithmetic unit. It contains N decider blocks 1c for performing operations on two numbers, control block 2, switch 3, N-bit register 4 of the operation end, block 5 of code comparison, N-bit shift register 6, block 7 of forming the result, N-1 delay elements 81. g of control bus 9 and input buses of operands 10 | -10 || (4.1. As decisive blocks, blocks are used that allow to combine in time the processes on bit input of operands and bit formation of the result, on. h: yn from the senior bits. To show the result in decisive points use an excess single-position positioning system whose digits are encoded as non-standard: the tO / l3 binary code from the everyday counting system are represented at the outputs of the decision blocks by single or zero signals on different buses, where cj, the number of digits (symbols) of the redundant system For a binary number system, with numbers, r, 6, ljj, the number of resolving blocks does not depend on the number of operations that make up the sequence (and is defined by the expression Vhr JhTiL where n is the operand -. dev, ah- the delay in the formation of the first bit of the result (expressed in the number of cycles) in the decisive blocks I (-IN after entering the first bits of the operands. For example, if, then after entering the first bits of the operands in the first step of calculating the first bit The results are obtained in two cycles, that is, in the third cycle. The outputs of each decision block 1j (,. N-1) are connected to the group of inputs of the decision block Ij + t, and the outputs of the decision block 1 yj are connected to the group of inputs of the decision block 1. The group of outputs of the control unit 2 is connected to the clock inputs of the block 7 for1 "1p result and to the clock inputs of the decision blocks, the outputs of which through the switch 3 are connected to the information inputs of the result generation unit 7. The output of the operation end register 4 is connected to the control inputs of the switch 3 and to the control input of the latter. one group of information inputs of code comparison unit 5, the second group of information1; the ionic inputs of which are connected to the outputs of shift register 6. The output of each j-th bit of shift register 6 (, N) is connected to the control input decision block, Ij, and the control input of the shift register b is connected to one output of control unit 2. The input buses of operands 10. and 102 are connected to two corresponding information inputs of the decision block If, and to one information INPUT of each decision block 1 (, N) through the delay elements 8J-I connected input bus operands. The control bus 9 is connected to the output circuit of the register 4 code at the end of the operation. The result generating unit 7 is a converter of the numbers represented by a consecutive redundant code into a non-redundant (canonical) number system. .. Suppose you need to perform a sequence consisting of k two-seat operations. If the number of operations forming the sequence is equal to the number of decision blocks, i.e. then the sequence of the iterations is performed in one cycle. If, however, the calculation process is conditionally divided into several cycles, in each of which no more than N operations are performed. In the first cycle of computations, the first bus group, including N + 1 operands, represented by a sequential code, enters the input busses of the operands lO -lOn + i. In subsequent cycles, the input bus operands lOj-lOK-n are received

: groups of N operands (in the last loop, the number of operands may be less than N).

In the initial state, in the first discharge of shift register 6, one is recorded, and in register 4 of the end of the operation, the unit is recorded in bit 5.

, ecAMK (modN) L N, if k (modN) 0.

in each i-M cycle of the first cycle, the input busses of the operands (+ j receive the i-e bits of the corresponding operands. Each decision block li-lf performs a certain operation, and

the control unit 2 generates the clocking signals for them. After the first h + 1 clock has been executed, the first bit of the redundant code of the first intermediate result is present at the outputs of the decision block 1. In the (h + 2) -M cycle, this bit begins to be processed in the decision block Ij, for which this bit is the first bit of one operand. Similarly named non-redundant code

the other operand for the decision block 25 12 comes from the output of the delay element 8j, which delays the bits of the operand by the same number of clock cycles as the decision block Ij, i.e. on h + 1 cycles. Subsequently, the discharge of the intermediate result obtained in the decision block begins to be processed in the decision block 1, etc., i.e. the bit of the intermediate result obtained in the i-th 35 clock cycle at the outputs of the decision block Ij is used as the next

the operand bit in the decision block on the (i + DM cycle. Each delay element 8 j delays the bits of the corresponding ,,, corresponding operands by j (h + l) cycles, thus ensuring the supply of bits of the operands to the input of the decision block Ij4i simultaneously with the discharge of the intermediate result, formed in the decision block Ij, which goes to the other information inputs of the decision block Ij + i. After the first n + h steps are completed, the decision block 1 j outputs the 12th (last) 12 the category of the first intermediate result, i.e. t perform the operation entrusted to him, in subsequent cycles decisive block 1 can process the bits of the intermediate result, -55, formed in the decisive block IN t

The number N is chosen such that by the time the first discharge of the intermediate result occurs, at the outputs gQ of the decisive block IK, the decisive block 1 is free.

This ends the first computation cycle.

The second cycle of calculus starts from the moment the first (intermediate) bit of the intermediate result arrives from the outputs of the decision block 1) to the inputs of the decision block 1 {. At the same time, the input buses of the Yuz-10 41N operands receive bits of the operands of the next group. The operation cycles of the device are repeated until the input buses of operands 10; won't accept operands of all k operations,

Simultaneously with the filing of the last group of operands, control signal 9 receives a signal, which is valid until the end of the operation of the device and which produces a register code 4 for the end of the operation. The number L of the register register 4 of the end of the operation, in which the unit is written before the beginning of the calculations, corresponds to the number of the decision block which in the last cycle performs the k-th operation in a given sequence of operations.

In each computation cycle, after performing h + 1 consecutive clock cycles, the control unit 2 signal shifts the unit in the shift register; ha 6 by one bit to the right, and as a result, the control input of the decision block ij is fed, a single signal from the bit output shift register 6. This signal is clocked by the signals of the control unit 2, arriving at certain clocking buses of the decision blocks, as a result of which the decision block 1J is reset to perform a certain operation immediately before the cycle The first bits of operands of this operation are received at its inputs.

Claims (1)

Thus, at the moment of forming the first bit of the intermediate result, a single signal is present in the decision block 1J at the output of the j-ro bit of shift register 6. В. After the last cycle of operation after shifting the unit to the bit with the number of the shift register 6, the decisive block begins the last operation in the specified sequence and at its outputs in each successive cycle there are next bits of the final result. Since in the initial state in the register 4 of the end of the operation, the unit is recorded in the bit with the number about, after shifting the unit in the shift register 6 to the bit with the number and block 5 of the code comparison gives to. the control input of the result formation unit 7 is a signal corresponding to the equality of the codes, which initiates: the operation of the result generation unit 7. In this case, the next bits of the final result from the outputs of the decisive block 1 y, through the switch 3, which is controlled by the register 4 ends of the operation, go to 1 informational ones; the inputs of the result form block 7, where the sequential batch of the final code is converted. Into a redundant parallel code (nSrimer, by summing up the codes of the digits of the redundant system of detections taking into account of the weights according to the rules of the inadequate numbering system, i.e. with the help of high-resolution transfers but). The operation of the responsebtaxa generation unit 7 is clocked by the signal of the control unit 2-k Total number of clock cycles, which is necessary for obtaining n digits of the end. the result in the proposed device is k (h. + l) + n-l. If the order of the operations forming the {{hr} dv_v_dv_v_v_p_p_p_p_p_p_p_p_p__p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_p_} p; Jim Ymeer, with and this is the value of 10; ..- l, - ;; :; ; - So. Ebm, Il |) edLaga € fOe device allows you to reduce the time. in terms of the sequence of 6px In addition, thanks to a random iyod and output of information, the decisive itybyy of the proposed device hinges not only the number of outlets and outcalls; h & y & Equality & pw: uter them in the form of large integral ckeM. Arithmetical device DL; execute 6 operations on: descale them with numbers containing N decisive blocks for performing 2 and 2 numbers, switch / code comparison unit, operation end register, pins of which are connected to the first group of switch inputs, control unit, first group the outputs of which are connected to the clock inputs of the decisive: blocks for performing operations on two numbers, and two information inputs of the first decision block for performing operations on two numbers are connected to the input It is consistent with the first and second operands, distinguishing it with the fact that, in order to increase speed, it contains a result formation unit, a shift register and N-1 delay elements, and the input j-ro (, Nl) delay element connected to the input bus of the (J + 2) -th operative, -a output - with the first information input (j + l) -ro of the decision block for performing two numbers, the output of which is connected to R with the second information input (j + 2) -ro A booster block for you. operations on: two numbers AND the corresponding input of the second group, pnbJ of the switch, and the output of the N-ro deciding unit to perform operations on two numbers of connections with the third | 1Information input of the first deciding | tse6 bLrya For performing operations on Two numbers, the output of the No.1outator the first input of the fürmirb ayi block is connected to the second input of the control unit; the output of the control unit is connected to the second input; the output of the comparison block, the first group of inputs of which is connected to the outputs of the end register of the operation, is connected to the third input. In addition, the group of inputs is connected to the corresponding shift register register and control inputs of the decisive units for performing operations on two points, the input of the shift register is one and one is connected to the output unit and the control unit.