SU661400A1 - Phase-to-code converter with automatic error correction - Google Patents

Description

(54) PHASE CODE CONVERTER WITH AUTOMATIC CORRECTION OF ERROR

The invention relates to the field of pulsed technology and can be used in the construction of high-precision and high-speed converters.

Phase-to-code converters are known with automatic error correction, in which the conversion result is corrected by periodically paralleling the channels. The accuracy of conversion in such devices is achieved due to the fact that the variable component of the voltage of the switching frequency at the output does not depend on the phase nonidentity of the channels. However, switching at the input voltage, the phase shift between which is to be measured, significantly reduces the speed of the converter, since the result is obtained by synchronous detection of the output voltage of the switching frequency, and the latter must be selected several orders of magnitude lower than the frequency of the input signals (to reduce the effect no phase jumps during switching) 1.

A disadvantage of such transducers is a large amplitude-phase error.

Phase-code converters with automatic error correction are also known, containing rectangular oscillators and two triggers that are triggered by opposite fronts of rectangular oscillations obtained from voltages, the phase shift between which is measured 2.

Their disadvantage is a high error due to phase nonidentity.

Phase-code converters are also known that contain a series-connected controlled phase shifter and a driver whose output is connected to one of the inputs of the first trigger connected by a second input to the output of the second driver, a quantizing converter connected to the trigger output, the second trigger, one input of which is connected through the first switch with the outputs of the first and second drivers, serially connected to the inputs of the device, the second switch and the auxiliary driver, switching An on-line generator connected to the control inputs of the switches and the first input of the synchronous detector is connected to a controlled phase shifter 3. Their disadvantage is a large amplitude-phase error. The purpose of the invention is to reduce errors due to the nonidentity of the main channels, and to reduce the amplitude-phase error of the converter due to the departure of the zero line of the auxiliary correction channel former. This goal is achieved by the fact that a phase-code converter with an automatic error correction, containing in one of the channels a series-connected controlled phase shifter and a driver, the output of which is connected to one of the inputs of the first flip-flop connected by the second input to the output of the second shaper, the output of this a trigger is connected to a quantizing transducer, the second trigger, one input of which is connected via the first switch to the outputs of the first and second drivers, as well as series-connected second a swivel switch connected to the device inputs and an auxiliary driver, a switching generator, the output of which is connected to the control inputs of the switches and the first input of the synchronous detector, an output connected to the control inputs of the switches and the first input of the synchronous detector, output connected to the controlled phase shifter It is equipped with an inverter, adder and a third trigger, one input of which is connected to the output of the first switch, the other input through the inverter is connected to the second input of the second th flip-flop and the third flip-flop output being connected to the first input of the adder, the other input of which is connected to the output of the second flip-flop. The output of the adder is connected to the second input of the synchronous detector, and the input of the inverter is connected to the output of the auxiliary driver. FIG. 1 shows a converter block diagram; in fig. 2 - time diagrams of his work. The converter contains a controlled phase shifter 1, shapers 2, 3 rectangular oscillations in the main channels. trigger 4, quantizing converter 5, auxiliary driver of 6 square-wave oscillations, inverter 7, triggers 8, 9, adder 10, synchronous detector 11, switching generator 12, and switches 13, 14. The device operates as follows. The phase-matched voltages U / and Ui (Fig. 2, a, b), without loss of generality, are shown in-phase, one directly and the other through the controlled phase shifter 1 affects the inputs of the formers 2 and 3 that produce the amplification and limitation of the input voltages . The voltage drops from the outputs of the formers 2 and 3 (Fig. 2, c, d) trigger a trigger 4, and the pulses from the output of the latter are encoded using converter 5. At the same time, the voltages Ui and U are controlled by an automatic switch 14 controlled by generator 12 , are alternately supplied to the auxiliary channel containing the shaper 6. If there is care of the zero line of the shaper 6 (shown by the dashed line), the porosity of the rectangular voltage of the latter is different from the line of the shaper 2 (Fig. 2e) and depends on the amplitudes of the input voltages. This voltage directly and through the inverter 7 is fed to the inputs of the flip-flops 8 and 9, to the other inputs of which, via the switch 13, the voltage comes from the output of the corresponding driver 2, if the auxiliary drip is supplied with the load lj (, and the driver 3, if IJj. Pulses with amplitude Uo from the outputs of the flip-flops 8 and 9 (Fig. 2, g, h) through the adder 10 are fed to the input of the detector I, controlled by the generator 12. Because the average value of the total voltage at the input of the detector I 1 is in both cycles switching is the same (), then ogp The frequency of the com mutations is absent and the voltage on B1 1 of this detector is zero (there is no control action for the controlled phase rotation of 1). When the position of the zero line of the driver 6 changes, for example, in the direction of increasing asymmetry (dotted line in Fig. 2. a, b moves farther from the abscissa axis) the edges of the pulses of the downstream driver 6 and, accordingly, the inverter 7 (in Fig. 2, e are indicated by arrows) are displaced. In this case, the displacement occurs to the same extent in different directions, as a result of which the duration of the pulses at the output of the trigger 8 increases, the fja output of the trigger 9 decreases, and the deadline their duration remains unchanged. Thus, the auxiliary correction channel turns out to be insensitive to the offset of the zero line of the former 6. If there is a mismatch between the phases of the input and output voltages of one of the main channels D U, leading to the error network (Fig. 2, d dashed line), this causes the fronts to shift pulses at the outputs of the flip-flops 8 and 9 in one direction (Fig. 2, g, h) and the change in the average value of the voltage at the input of the detector 11 in this cycle. As a result of the appearance of the switching envelope frequency, the output voltage of the detector becomes different from zero and affects the phase shifter 1 in the direction of decreasing D U, i.e., the error of the main channels is corrected. At the same time, as noted above, the zero-line drifts of the driver 6 of the correction channel have no effect.

Claims (2)

1. USSR author's certificate No. 176329, G 01 R 25/04, 1965. 2. USSR Author's Certificate No. 121871, G 01 R 25/00, 1969. H Lt () tact FIG. 2