SU656063A1 - Device for automatic checking of digital objects - Google Patents

Description

a random test may be different even if the monitored object is completely corrected. It is also possible that, due to critical conditions in the reference object, its reaction coincides with the reaction of the faulty object. As a result, a serviceable object may be incorrectly rejected, and a faulty object is recognized as valid.

The closest technical solution is a device for automatic control of digital objects, comprising a test generator, an input signal shaping unit, a reference block, an output discriminator, a comparison block, a block, a clock counter, a control block, the first, second, third and fourth outputs of the block the controls are connected respectively to the input of the test generator, to the first input of the input signal conditioning unit, to the first input of the blocking block, to the input of the clock counter, the first three gene input The test generator is connected to the second input of the input signal generation unit, the third input of which is connected to the first output of the blocking unit, the output of the input signal conditioning unit is connected to the input of the reference unit and the device output, the device input is connected to the output discriminator input of the output signals, the output of which is connected to the first the input of the comparator unit, the second and third inputs of which are connected respectively to the output of the reference unit, with the second output of the blocking unit, the output of the comparator unit is connected to the input of the unit management 3.

The disadvantage of the prototype device is the high cost of equipment. For each object to be checked, it is necessary to create its own ternary model, in which instead of the usual binary elements, special elements are used, which work in the Eichelberger ternary logic. The complexity of this model exceeds the cost of the simulated object.

Another disadvantage of the known device is that for many types of objects the Eichelberger trinity modeling gives an incorrect result. Ultimately, this leads to a false fixation of an uncertain state on many outputs of an object on almost any test, which essentially excludes the possibility of testing such objects on pseudo-random tests. More accurate methods for the detection of critical con fi guration and risk in digital circuits require, respectively, more complex (for example, octal) simulation, which can only be implemented by software on a computer, i.e., the equipment costs in the respective models exceed reasonable limits.

This lack of ternary modeling leads to the fact that the known

the device is applicable for a relatively narrow class of objects.

The aim of the invention is to simplify the known device.

The goal is achieved by the introduction of a memory unit, an input unit, an address selection unit, the fifth and sixth outputs of the control unit are connected respectively to the first input of the address selection unit and to the first input of the memory unit,

the second and third outputs of which are connected respectively to the second input of the address selection block, to the second input of the test generator, to the second input of the blocking block, the output of the input block is connected to the second

the input of the memory block, the output of the counter, clock cycles is connected to the third input of the address selection block, the output of which is connected to the third input of the memory block.

The information that is entered into the specified memory block is obtained on the basis of a software simulation of the object using a computer on the selected pseudo-random test. In this case, any modeling method most suitable for the given object can be used, providing

detection of critical constants with combinations of delay elements that are actually possible in the object.

The drawing shows a block diagram of the proposed device.

Control device of digital objects

contains test generator 1, an input signal forming unit 2 connected to it, having outputs for connecting to the inputs of a controlled 3 and reference 4 blocks and intended for storing

the logical values of the signals applied to the inputs of the objects and the formation of the potentials corresponding to these signals, the discriminator of the output signals 5, which provides control of the output potentials of the object being monitored to match the potentials of the logical values "1 and" O connected to the outputs of the discriminator 5 and the reference unit 4, the comparison unit 6 , which serves to detect the logical inequality of the output signals of the monitored and reference blocks, the block of block 7, prohibiting the block of comparison 6 to take into account when comparing the outputs whose state is an indeterminate clock counter 8, fixing the current test clock number, control unit 9,

memory block 10, which provides storage of information about the state of conclusions in the corresponding test cycles and connected to address selection block 11, which provides for receiving, storing and issuing information

Claims (3)

1. USSR Author's Certificate No. 378852, cl. G 06 F 11/00. 1967. 2. US Patent No. 3,614,608 324-73 1972. 3.Patent of Germany No. 2121.115 21 e 31/28, 1975.