SU1287164A1 - Device for checking digital units - Google Patents

Abstract

The invention relates to computing and can be used to control digital objects. The aim of the invention is to increase the depth of control by providing control of the i-ro process (, ..., n, where n is the number of control points of the monitored block) within the specified allowable limits of variation. The device contains a synchronization unit 5, a test generator 1, a node 2 of communication with an object, a comparison circuit 4, a reference block 3, a switch 6, a switch 7, an indication block 8, a switch block 9, a digital-analog converter 10, the first and second threshold elements 11 and 12, the first and second multivibrators 14 and 15, the element NOT 13, the elements AND 16.1 and 16.2, the element 11Ш 19, the element BL-HE 18, the element 20 switching (with three stable states). The device allows to check for the presence of between signals in the circuit of the monitored unit. 2 Il. S (l

Description

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The invention relates to computing and can be used to control digital blocks.

When designing digital blocks, it is not always possible to take into account the scatter and fluctuation of the temporal characteristics of the signal transmission circuits, which randomly determines the correct and incorrect sequence of signals, thereby causing the simulations of the signals (races) of these signals that are unstable. .

 The purpose of the invention is to increase the depth of control by providing control of the i-ro process (, ..., p), n is the number of control points of the digital block being monitored) within the specified allowable limits of variation.

FIG. 1 shows a block diagram of the proposed device; in fig. 2

timing diagram of the formation of the delay signal.

The device (Fig. 1) contains a test generator 1, a group of potential matching nodes 2, a memory block 3

reference, comparison circuit 4, synchronization unit 5, switch 6, device operation mode bus 7, indication unit 8, change limit task bus 9 of the device's controlled i-ro process, digital-analog converter (CDL) 10, threshold elements 11 and 12, the element NOT 13 multivibrators 14 and 15, the elements AND 16 and 17, the element OR-NOT 18, the element OR 19, the switching element 20.

Tests for which a digital block is checked do not reveal the presence of a complex (race) between different signals in the block circuit. The presence of contests (races) leads to the appearance of unstable faults (malfunctions) during the operation of the unit. Therefore, a unit tested only by functional tests may have difficult to diagnose failures during operation. The monitoring device allows to detect the presence of contests (races) between different signals in the chains of the monitored block, due to the artificially introduced delay of the signal participating (or suspected of participating) in the sessions, races. The signal race is described in the case when the signals are shifted relative to each other for a small time at, usually measured within one or two

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in, x

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ten nanoseconds. Then, the spread and fluctuation of the characteristics of the signal paths (delays and fronts of digital elements) may lead to 5 changes) the sequence of the signals:

races, and, consequently, to failure (the spread and fluctuation of delays and fronts of digital elements, as shown by the experience can shift the signal within one to two tens of nanoseconds).

“Therefore, the amount of artificially introduced delayed signals for detecting races does not exceed several tens of nanoseconds. If a failure occurs within these limits for a delayed signal, it is concluded that the suspect signal is participating in the race. If the fault does not occur, then the value of the artificially introduced delay does not increase, and the signal is considered not

 suspect

racing

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Thus, the limited amount of the artificially introduced delay of the signals allows to reveal the true signal races in the digital block chains.

. The designation of individual elements of the device. DA 10 is designed to convert the value of the input delay, specified in binary code, into an analog signal (voltage) and can be implemented, for example, on 572PA1A microcircuits.

Threshold elements 11 and 12 are needed to set the signal levels between which the signal should be delayed. Threshold elements can be implemented, for example, on the IC 521CA1.

Multivibrators 14 and 15 are designed to generate pulses, the duration of which determines the magnitude of the artificially introduced signal delay, and the paralysis time of the multivibrators exceeds the duration of the input delay.

Three steady state switching element 20, functioning as bidirectional signal conditioners, is designed to interface the monitoring device and control point of a digital unit on which an artificial signal delay is introduced (can be implemented, for example, on K589AP16 chips) .

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The device works, as follows.

The test generator 1, under the action of the synchronization unit 5, generates verification tests that are applied to the test unit through group 2 of nodes. The reaction of the block goes through nodes 2 to the circuit 4 of comparison. The unit 3, under the action of the sync signals of the synchronization unit 5, reads the response values corresponding to the operable unit to be checked. On bus 9 in binary code, the value of the artificially introduced delay of the signal that is suspected of participating in the status is set. In this case, the output of element 20 is connected to the control point of the monitored unit at which the suspect signal is located. The delay of this signal is carried out as follows (FIG. 2).

The delayed signal is fed to the inputs of the threshold elements 11. and 12 When the signal reaches the level - er -. threshold element 11 (this level corresponds to the logic level O), threshold element 11 is triggered. Under the action of a positive differential, the multivibrator 14 absorbs a pulse whose duration is determined by the voltage supplied to the input of the multivibrator 14 from the DAC 10 output, which converts the specified delay value from binary code to direction. As a result, the output of the element AND-NOT 18 forms a level of logical O, which, acting on the control input of the element 20, transfers it from the third non-indifferent state to the state allowing the input signal on the information output to pass to its output. the input, and since the output of the element OR 19 is formed the logic level O then the output of the element 20 appears the level of logical O,

Therefore, the rise of the leading positive edge of the suspected signal is stopped, and instead the logical O level is set. On the falling edge of the pulse generated by the multivibrator 14, the logical level 1 is set at the output of the OR-HE element 18, thereby translating the element 20 in the third (indifferent) state. And only then begins

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the rise of the forward positive edge of the suspected signal, caused by the delay of the leading edge, - by the value of m - the duration of the impulse produced by the multivibrator 14.

As the leading edge increases, the delayed signal reaches the trigger level of threshold element 12 (this level corresponds to the logic level 1).

It should be noted that when the leading edge of the delayed signal of the logic level O is reached, the first threshold element 11 does not work, since the paralysis time of the multivibrators 14 and 15 exceeded the duration of the artificially introduced delay.

When the leading edge of the delayed signal reaches the logical level 1, the threshold element is triggered, but since its output signal is inverted, the multivibrator 15 does not trigger, and the delayed signal continues to rise to the upper level of the suspected signal. Then a rear suspect signal is formed. When the falling edge reaches the logical level 1 (the trigger level of the threshold element 12), the threshold element 12 triggers and the multivibrator 15 generates a pulse whose duration is determined by the voltage supplied from the DAC output 10, which determines the delay dT of the trailing edge of the suspected signal (obviously that the delay values of the front and rear edges are the same).

As a result, the output of the element OR NOT 18 forms the level of the logical O, which, acting on the control input of the element 20, again transfers it from the third (non-different) state to the state allowing the input signal to pass to its output . Since at the output of the element 1 of the software 19 a level of logical 1 is formed, the level of the logical 1 appears at the output of the element 20. Therefore, the falling edge of the trailing edge of the suspected signal stops, and instead

set the logical level

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By the hall, it is the front of the pulse generated by the multivibrator 15 on the

during the OR-NOT 18 element, the logical level 1 is set, thereby translating the element 20 into the third non-relevant state. And only then the falling edge of the suspect signal begins. Thus, the trailing edge of the suspect signal is delayed by At. As a result, the suspect

the signal is completely delayed by a delay value d g.

The detection of the presence of status is carried out as follows. The output of the switching element with three stable states of the element 20 is connected to the point of the controlled object where the suspect is located

status is x

signal (it can be a circuit of an object of control). Then the delay value of this signal is set, and the test generator 1, under the action of the synchronization unit 5, generates verification tests. In case of coincidence of the reference reaction and the reaction of the block. for all tests at a given delay, a new large delay value is set, and all tests are again checked. The limits of variation in the magnitude of the delay are determined by the specific type of logic block, which determines a certain spread and fluctuation of the temporal characteristics of its circuits.

If within the specified limits of the signal delay variation the testing of all tests is carried out, then

 signal n

in otherwise

In this case, a conclusion is made on the presence of the component and its location, which allows for the appropriate adjustment of the circuit design of the monitored unit. Thus, when connecting to various points of the monitored block, it can be completely checked for the presence of a status that the suspect is involved in

If we consider the input combination (00) at the direct inputs of the And 16 and 17 elements, then we can see that in this case O and, therefore, the output will be present at the outputs of both the And 16 and 17 elements. OR 18 will be 1 which translates element 20 into an indifferent state. This circumstance is used in the scheme of the device that illustrated

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Van time diagram in figure 2. In this case, the input combination 00 cannot be considered as forbidden, since this code is fed to the inputs of AND elements 16 and 17.

Thus, the elements AND 16 and 17 and the element OR NOT 18 provides the formation of the signals presented on the timing diagram.

It should be noted that the presence of a constant logical 1 at the output of the element OR 19 is valid only for the three input combinations 00, 01 and 11. If there is a fourth remaining input combination 10 at the output of the element OR 19 there will be a logic level O (the input signal equal to logical 1 at the first input OR 19 is inverted and OR adds two input signals equal to the logical O).

Thus, the element OR 19 provides the formation of the signals shown in the timing diagram in FIG. 2

Claims (1)

Invention Formula Digital control device blocks, containing a synch block; memory, a comparison circuit, a display unit, a switch, a test generator, an etalon memory block, the first output of the synchronization unit connected to the synchronous input of the test generator, the second output of the synchronization unit of a reference, the output group of which is connected to the first group of circuit inputs Comparison, characterized in that, in order to increase the depth of control by providing control of the i-ro process (i-1, ..., p, p. is the number of control points of the monitored digital block) within the specified allowable limits of variation, the device contains a group potential matching nodes, digital-analog converter, two threshold elements, NOT element, two AND elements, YLI-NOT element, OR element, switching element, and two multivibrators, with a group of test generator outputs connected to the first group of inputs of sweat nodes The group of cells, the first group of outputs of which is connected to the group of information inputs of the monitored digital block, the group of outputs of which is connected to the second group of information inputs of the potential matching nodes of the group, the second group of outputs of which is connected to the second group of inputs of the comparison circuit and the output unequally connected to the information input of the switch , the output of which is connected to the information input of the display unit, the group of information inputs of the switch is connected to the limit setting bus changed controlled by the i-ro process of the device, as well as to the information inputs of the digital-analog converter, the output of which is connected to the inputs of setting the pulse width of the first and second multivibrators, the output of the first multivibrator is connected to the forward input of the first And element and inverse the input element OR, the output of which is connected. with information ten 15 20 the input of the switching element, the control input of which is connected to the output of the OR-NOT element, the first and second inputs of which are connected to the outputs of the first and second And elements and inverse inputs of the second and first And elements respectively, the output of the switching element is connected to the inputs of the first and second threshold elements and is connected to the i-th control point of the monitored digital block, the output of the first threshold element is connected to the trigger input of the first multivibrator, the output of the second threshold element is connected via el NOT with the start input of the second multivibrator, the output of which is connected to the direct input, second house AND and the front input OR, and the control input of the switch is connected to the device operation bus.