SU587507A1 - Shift register - Google Patents

Description

one

The invention relates to automation and computing, and is intended to construct quaistatic registers with parallel-sequential recording of information.

Shift registers on MDPtransistors are known, in which synchronous writing to bit cells is performed only in the absence of i-act Sigti OB on the corresponding buses.

The closest to the technical essence of the invention is a shift register containing a quasistatic trigger consisting of two series-connected inverters, the input and output of which are connected to the first matching cascade, the input of the first inverter is connected through the second matching cascade to the input bus, and the output - with the third matching stage, the inputs of the matching stages are respectively connected to the first control buses, and the third inverter 2.

However, these devices do not allow building shift registers with parallel-sequential writing.

The purpose of the invention is to expand the scope of the register.

For this, the device contains three keys, the first of which is connected to the third matching stage, the third inverter and the second key, the inputs of the first and second keys are connected to the second control buses, the third key is connected to the output of the third inverter and the code bus.

FIG. 1 is a schematic diagram of the proposed register in FIG. 2 - time diagrams of his work.

The shift register contains a quasistatic trigger with one intermittent

connection, consisting if3 of two series-connected inverters 1 and 2 and the first matching stage 3, the second matching stage 4, the third inverter 5, the third matching stage

6, input 7 and output-8 tires, first control buses 9 and 10, respectively, power bus 11, keys 12, 13 and 14, second control buses 15 and 16, code bus 17 and common bus

food 8.

The operating principle of the shift register is explained by voltage and output timing diagrams for the case of using p-channel MOS transistors and supplying the circuit from a negative voltage source, where 19 and 20 are control signals, 21 and 22 are second control signals, 23 - The signal on the input bus 7, 24 is the signal on the code bus 17 and 25 is the signal on the output bus 8.

In the sequential information recording mode, a high level of negative voltage is supplied to bus 16, key 12 is in the open state, and busses 15 and 17 receive a zero voltage level that ensures locking keys 13 and. 14 .

With the arrival of the first control signal on buses 9 and 10, the matching stages 3 and b are closed. In this case, one cross-link of the quasi-static trigger is broken and the input of the third inverter 5 is disconnected from the output of the first inverter 1, which ensures that the output bus 8 maintains the voltage level corresponding to the cell state before the arrival of the clock signals, due to the charge stored on the input parasitic the capacity of the third inverter 5; the second matching opens cascade 4, through which: the signal present on the input bus 7 is fed to the input of inverter 1. At the end of the first control signal, the second matching cascade 4 closes and the matching cascades 3 and b open, which provides a cross connection of the inverter 1 and 2, forming a trigger, and connecting the third inverter 5 to the output of the first inverter 1. In this case, the output bus 8 sets the voltage level corresponding to the new logic state written to the cell during operation clock signals.

In the parallel code writing mode, a zero voltage level is applied to bus 16, locking key 12, and bus 15 - a code recording enable signal (high negative voltage level) that opens key 13. In this case, the input of inverter 5 is disconnected from the output of inverter 1 and through the key 13 is connected to the common bus. Since the lower transistor of the third inverter will be locked in this case, the voltage level on the output bus 8 will be determined only by the state of the key 14, which is controlled by the signal On the code bus 17. Thus, regardless of

The state of the quasistatic trigger on the output bus. The cells are set to a logic level corresponding to the inverted code signal 24 on the code bus 17, which is rewritten to the next cell when the clock signals arrive.

The code signal to the bus 17 should be supplied only if there are inverse and direct resolution signals for address polling on the second control buses 16 and 15. In the sequential polling mode, the code bus 17 is supplied with a zero voltage level corresponding to a logic zero.

FIG. 2, the first two clock signals correspond to the mode of sequential recording of information, and the last two signals correspond to the mode of parallel recording of information in a cell.

To manufacture a register with parallel-sequential recording of information based on the proposed cell, any standard technology of MIS structures with a p or n channel can be used.

Claims (2)

1. Author's certificate №342223 Cl. Q 11 C 19/28, 06.72. 2. US Patent No. 3406346, cl. 328-37, 04.20.66. rr-p F-I Yy