SU832726A1 - Address register - Google Patents

Description

one

The invention relates to semiconductor electronics, electronic and computer technology and can be used in the construction of storage devices on CMOS transistors.

An address register is known that contains an input key, a clocked RSrf trigger, an initial state recovery circuit, and a source of reference voltage.

The disadvantage of this device is the design complexity associated with the necessity of using a reference voltage generator.

The purpose of the invention is to simplify the design and increase reliability.

The goal is achieved by the fact that in a device containing an input key MOS transistor, a trigger on CMOS transistors, an installation MOS transistor connected between one trigger input and a common bus.

An inverter and a clocked OR-NOT element on CMOS transistors are introduced, the inverter input is connected to the bus not the selection signals, and the output to the clock input of the clocked element OR NOT, one input of which is connected to the forward one, the second to the inverse output of the trigger and the output is to the gate of the input key MOS transistor.

The drawing shows the principal electrical circuit of the address register on CMOS transistors.

The address .pjerHCTp on CMOS transistors contains an input key on transistor 1, clocked by RS flip-flop 2

5 on transistors 3-7, a restoration circuit of the initial state on the transistor 8, a synchronizing device consisting of a series-connected inverter 9 on the transistors 10 and P and a clocked element 12 ORINE on the transistors 13-16, the input I7 of the address signal (compatible with TTL ), selection signal input 18 (CMOS level),

Direct 19 and 20 inverse of the address signal.

The input 17 of the address signal through the transistor 1 of the input key is connected to the right shoulder (output 19) RS-TpHrrg-i pa, which is the forward output of the address signal, and the first input of the clocked element OR NOT (the gate of the transistor 13), the second input which (gate of the transistor 14) is connected to the left shoulder (output 20) of the trigger, which is the inverse output of the address signal. The gate of the transistor 1 of the input key is connected to the output 21 of the clocked element OR NOT connected to the drain of the transistors 13-15, and the source of the p-channel transistor 15 is connected to the power source Uj, and the sources of the p-channel transistors 13 and 14 -channel transistor 16, the source of which is connected to a common output. The input of the inverter 9 is the gates of transistors 3 (RS-Trigger) and 8 (recovery circuits) connected to the input of the select signal, and the output 21 of the inverter is connected to the clock input of the OR-NOT element by the gates of transistors 15-16.

The address register works as follows.

In the initial state, the input key on the transistor 1 is open, because the selection signal has a high level, therefore, the output of the inverter 9 is low, the transistor 15 is open and the output voltage of the clocked W-NOT (output 21) is equal to the source voltage nutrition

The voltage at the output 22 of the RS flip-flop 2 and the direct output of the inverter 9 is equal to the voltage at the input 17 of the address signal. The recovery transistor 8 is open, and the voltage on the left side of the B5 trigger, which is the inverse output 20 of the address signal, is ON.

When a low level is applied to the input 18 of the select signal chip, the restoration circuit transistor 8 is closed and the transistor is opened. 3 RS triggers. In this case, the output 22 of RS-TpHr Gera is connected via an open transistor 3 to a power source. When the selection signal passes through the inverter 9, the transistor 15 closes and the transistor 16 "opens.

If a high level signal is applied to input 18 of the select signal, the open transistor 4 limits the charge of the parasitic capacitance (output 20), and

The capacitive capacitance at address 19 is charged through the open transistor 5,

IL to power supply voltage U Simultaneously with the appearance of a signal

a high level at the direct output 19 of the address signal opens the transistor 13, and the output 21 of the clocked element OR NOT sets the voltage O B, as a result of which

0, the key is closed, and the address register is disabled by the input 17 of the address.

If in the initial state, a low level address signal is applied to input 17, when a signal is applied to input 18

5 of the low level selection, the voltage at the output 19 is kept low through the open input key on the transistor 1, and the output 20 through the open transistor 6 is set to a voltage equal to the voltage of the power source. Simultaneously with the appearance of a high level signal at the inverse output of the 1 address signal. 20, the transistor 14 is opened, and the output of the clocked element OR-NOT is set to the voltage O B, as a result of which the input key is closed and the address register is turned off at the address 17 of the address.

The invention provides a simplification of the design of the address register and the memory circuit as a whole, as it allows reducing the number of signals required / for the operation of the address register, and hence the number of metallization and the area of the memory crystal.

Claims (1)

The invention of the Address Register, ss) holding the input key MOS transistor and Urigger on CMOS transistors, us0 {first 1 MOS transistor, connected between one trigger input and a common bus, which is that, in order to simplify the device and increase reliability, 5, an inverter and a clock element of the W-NOT on CMOS transistors are additionally introduced into it, the inverter input is connected to the bus of the selection signals, the output to the clock input 0 of the clocked element OR NOT, one input of which is connected to the direct one, the second to the inverse E | rcode of the trigger, and the output to the gate of the input MOS transistor. 5 Sources of information taken into account during the examination 1. Electronics, 1978, No. 14, p. 38 (prototype.