SU641633A1 - Mds transistor-based flip-flop - Google Patents

Description

I

The invention relates to a pulse technique, can be used in the construction of digital integrated circuits on MDPtransistors.

A quasistatic trigger on MIS transistors is known, which contains key traisistors, and the drain and the gate of the key transistor of one shoulder of the trigger are connected to the gate and drain of the key transistor of the other shoulder of the trigger.

The disadvantages of the known device are low speed, high current switched in the write bus, a large area of uncertainty of the trigger state (the whole write cycle) during which the average information is erased.

A quasi-static trigger on MOS transistors is known, which contains a storage capacitor, storage clocks and serially connected load transistors in each arm, drain and gate of which is connected to the power bus, the key transistor, the drain and gate of the second shoulder are connected respectively to the gate and drain of the key transistor and the control transistor in the first shoulder, and

in the second arm there are two parallel-connected control transistors, one of which has a gate connected to the input bus and the other to the write bus; The sources of the control transistors are connected to a common power source.

This device is difficult because of the presence of clock tires, which occupy a large area of the crystal with an integral design. In addition, a certain connection is required between a clock pulse and a write pulse, which imposes a restriction on its use in asynchronous devices;

The purpose of the invention is to simplify the trigger and expand its scope.

Claims (1)

To achieve this goal, in the first shoulder of the trigger on MOS transistors containing a storage capacitor and in each arm are series-connected load transistor, the drain and the gate of which are connected to the power bus, the key transistor, the drain on the gate of which are connected respectively to the gate of the key transistor of the second a shoulder, and a control transistor in the nerve shoulder, and in the second shoulder, two parallel-connected control transistors, one of which has a gate connected to the input bus and the other the recording bus, the sources of the control transistors are connected to the common bus, two parallel-connected transistors are introduced, one of which has a gate connected to the write bus, and the other has an input rail, the source of the one and the drain of the other is connected to one lining the storage capacitor, the other lining of which is connected to the common bus and the drain of one and the source of the other is connected to the recording bus. The drawing shows the trigger scheme. The power bus 1 is connected to the drain and the gates of the load transistors 2, 3, the output 4 is connected to the source of the transistor 2, the drain of the key transistor 5 and the gate of the key transistor 6 of the second arm. The output 7 is connected to the source of the transistor 3, the drain of the transistor 6 and the gate of the transistor 5 first arm, the source of the transistor 6 is connected to the drain of the control transistor 8, 9, the source of the transistor iO, the sources of the transistors 8-10 are connected to the common bus 11. The gate of the transistor 10 is connected to one plate of the storage capacitor 12, the other plate of which is connected to the common bus AND, to the drain of the transistor 13 and the source of the transistor 14. The write bus 15 is connected to the gate of the transistor 8, the source of the transistor .13, the drain and shutter t the ranzistor 14, the input bus 16 is connected to the gates of the transistors 9 and 13. The device operates as follows. In the storage mode on the write bus 15, a high voltage level, the control transistors 8 and 10 are open, the storage capacitor 12 is charged through the transistor 14 And through the transistor 13, if the input bus 16 has a high voltage level. In this case, the trigger is in one of two stable states. Writing information to the trigger is as follows. In the recording mode on bus 15 - low voltage ram; the control transistors 8 and the transistor 10 are locked due to the discharge of the storage capacitor 12 through the transistor 13, if there is a high voltage level on the input bus 16 and, accordingly, on the gate of the transistor 13. equal to the voltage of a logical unit. The key transistor 5 is locked at the source, and the source of the key transistor 6 is connected to the common bus 11 via the open control transistor 9. On the output bus 4, the voltage corresponds to the voltage of the logical unit, and on the output bus 7 - the voltage of the logical zero. If the input busbar 16, is a logic zero voltage, the transistor 10 remains open due to the fact that storage capacitor 12 cannot be discharged through the transistor 13 closed at the gate 13. Transistors 8 and 9 are locked because a low voltage level at the gate of transistor 8 recording area, and on the gate of the transistor 9 - the voltage of logical zero. Transistor 6 is locked by the source, and on the output bus 7 is the voltage of the logical unit, and on the output bus 4 is the voltage of the logical zero. The trigger eliminates clock signals for charging the storage capacitor, there are no restrictions on the moment of recording information, which simplifies the device and expands its scope. The invention of the trigger on MOS transistors containing a storage capacitor and in each arm of a series-connected load transistor, the drain and gate of which are connected to the power supply, the key transistor, the drain and gate of which are connected respectively to the gate and drain of the key transistor of the second shoulder, and control a transistor in the first arm, and in the second arm - two parallel-connected control transistors, one of which has a gate connected to the input bus and the other to the write bus, the sources of control Transistors are connected to a common bus, characterized in that, in order to simplify and expand the field of application, two parallel transistors are inserted into the first trigger arm, one of which has a gate connected to the write bus, and the other with an input width, the source of one and the drain of the other is connected to the gate of the control transistor and to one plate of the storage capacitor, the other plate of which is connected to the common bus, and the drain of one and the source of the other are connected to the recording bus.