SU566332A1 - Pulse expander - Google Patents

Description

The invention relates to measuring and computing techniques and can be used to extend the duration of input pulses by an integer number of times.

. Known devices for expansion

pulse durations; containing a pulse shaper, a trigger, a transducer, an equation device and a cumulative element ll.

The disadvantage of such a pulse expander is a limited range of output pulse durations.

Of the known devices, the closest in technical essence is a pulse spreader comprising a reversible counter, a counting pulse generator, a frequency divider, two AND elements, an OR element, and a trigger 2.

However, such an expander changes (distorts) the pulse repetition period with variable duration. This is due to the fact that at the output of a known expander a transformed pulse appears only at the end of the input pulse, and at the same time each converted pulse

delayed by the device for a time equal to the duration of the corresponding input pulse. If the duration of the input pulses varies from pulse to pulse, then the position in time of the converted pulses changes accordingly. For example, if a sequence of pulses with a variable duration but with a constant period (periodic sequence) arrives at the input of a known pulse expander, then a non-periodic sequence will be formed at its output.

The purpose of the invention is to reduce the distortion of the repetition period of the output pulses.

Claims (2)

This is achieved by the fact that in the pulse expander, the contents of the first and second elements I, the frequency divider, the generator of counting pulses, the output of which is connected to the first input of the first element I directly and to the first input of the second element I through a frequency divider, trigger, the first input of which connected to the second input iiepBoi o of the element I and to the input bus, and the output connected to the second input of the second element And, a decoder is entered, the inputs of which are connected to the outputs of the inverter counter and the output connected to the second input trigger Device zaderzhkiG-input coupled to an output of the second AND gate, and vgeod coupled to a subtraction input p versivnogo counter summiruyushy input coupled to an output of the first elemeyta IV The drawing is a block circuit diagram of the pulse expander.,. It contains generator 1 counting impool | Owls, elements 2 and 3, divider 4 repetition frequency of counting pulses, re) 38rc8 counter 5 with summing input 6 and subtracting input 7, decoder 8, trigger 9 and delay device 1O "Input 11 pulse expander connected to the first input of the element I 2 and with the first input of the trigger 9. The output of the generator 1 of the counting pulses is connected through the element AND 2 to the summing input of the reversible counter 5, and through the frequency divider 4, the element 3 and the delay device 1O to the subtractive input 7 of the reversible counter 5, the outputs of which through descrambler zero 8 subkey us to the second input flip-flop 9. The output trig-. Hera 9 is the output 12 of the device and is located on the other input of element 1-1 3. The pulse expander operates in the following way. The input pulse, which must be expanded, from input 11, goes to the input of the And 2 epement, with the help of filling the counting pulses of generator 1 (the frequency of the counting pulses Tj). Thus, with "al to be expanded, it converts into a series of counting pulses, the number of which is K - where tj is the size of the second impulse. These pulses are delivered to the summing input 6 of the reversing counter 5. Parallel to the input pulse by the leading edge; , flips trigger 9 to one state. From this moment on, the output pulse 12 (the pulse expander begins to form an output pulse, and a permitting voltage appears at the input of the element I 3. As long as the trigger 9 remains in the unit state, the counting pulses from the output of the 4 frequency divider with the Frequency following Tj passes through the FM element and the delay device 10 to the subtracting input 7 of the reversible counter 5. A delay device Yu is needed to shift the pulses in time to summing 6 and subtracting 7 inputs of the reversible counter 5. After vToro, as the number of pulses The owls delivered to the live exit 7 of the counter 5 will be equal to N, 5 will be completely cleared and at the output of the decoder 8 there will be a pulse, the potential rotating the trigger 9 into the initial (zero) state. As a result of a double flip of the trigger 9, its output will form impulse duration -. The expansion coefficient of the device 5 Pi. tlF, Thus, the expansion coefficient does not depend on the frequency of the counting pulses, and is determined by the division factor of the 4 frequency divider. The use of new elements — a decoder and a delay device — eliminates the distortion of the repetition period for pulses with a variable duration — and expands its scope. In addition, extended pulses are generated at the output of the device without a time delay with respect to the input pulses, which allows to increase the speed of imeryoNelnyh systems that use pulse duration expanders. DETAILED DESCRIPTION OF THE INVENTION A pulse extender comprising a reversible counter, the first and second And elements, a frequency divider, a counting pulse generator, the output of which is connected to the first input of the first And element, and to the first input of the second And element through a frequency divider. the trigger, the first input of which is connected to the second input of the first element I and the input bus, and the output is connected to the second input of the second element I, which is because, in order to reduce the distortion of the repetition period of the output pulses, a decoder is inserted into it, the inputs of which are connected to the outputs of the reversible counter, and the output connected to the second trigger input, a delay device whose input is connected to the output of the second And element, and the output connected to the subtracting input of the reversible counter, the summing input of which is connected output of the first element I. Sources of information received note in the examination 1, USSR Author's Certificate № 390661, cl. N OZ K 5/01, 1971. 2.Avtorskog certificate of the USSR № 455469, k. H 03 K 5/04, 1972.