SU750714A1 - Pulse repetition frequency multiplier - Google Patents

Description

(54) MULTIPLE OF FREQUENCY FOLLOWING PULSES

This invention relates to digital computing and can be used to multiply the frequency of a master oscillator. A device is known that contains in series connected doubling of the impu- sion following frequencies: gs, each of the doublers contains a standby multivibrator, the direct and inverse outputs of which through differentiating chains are connected to the inputs of a logic element, the output of which is connected to the input of the waiting multivibrator entering the composition of the subsequent doubler 1. The disadvantage of this device is a significant fluctuation of the phase of the output pulses. A pulse frequency multiplier is also known, containing N serially-connected multivibrators 2. A disadvantage of this device is also the low phase stable output signal of the device. The object of the present invention is to increase the phase stability of the output signal of the device. The goal is achieved by the fact that the device containing N (where N is 1, 2, 3, ..., W) of sequentially connected multivibrators is entered with an AND-NOT logical element, two unequalities and a trigger, the counting input of which is connected to the output N th multivibrator, the input of the first multivibrator is connected to the output of the first unequal element, one input of which is connected to the trigger output and the other. Its input is connected to the first input of the second unequality element and the input signal bus, the inputs of the AND-NOT element Eny with the outputs of odd multivibrators, the output of the element AND-NOT connected to the second input of the second element unequalities. FIG. 1 is a block diagram of a pulse frequency multiplier; in fig. 2 - time diagrams of his work. The pulse frequency multiplier contains in series connected multivibrators 1 ... 5, elements 6 AND-NOT, trigger 7, elements 8, 9 of unequalities, and

the counting input of the trigger 7 is connected to the output of the multivibrator 5, the input of the multivibrator 1 is connected to the output of the unequal element 9, one input of which is connected to the output of the trigger 7, and its other input is connected to the first input of the unequal element 8 and the input signal bus 10, element b AND-NOT connected to the outputs of all multivibrators 1 ... 5, the output of the element b AND-NOT connected to the second input of the element 8 is unequal-valued, the bus 11 of the output signal is connected to the output of the element b, the bus 12 of the output signal is connected to the output of the element 8 n equilibrium. I The pulse frequency multiplier operates as follows.

In the initial state with no input pulses (Fig. 2 a) at the outputs of the waiting multivibrators 1-5, trigger 7, unequal element 9 (Fig. 26, c, d, e, f, h, h) the level of the logical unit (high potential). At the output of element 6, AND-NOT (Fig. 2 and), element 8 of unequalities (Fig. 2 k) is a logic zero level (low potential). The input-sequence of pulses of a logical unit with a duty cycle of two is fed to bus 10. When When the input pulse of the logic unit level arrives at the input of the multiplier (Fig. 2a, moment to), since there are high potentials at the inputs of the logic element 9 (Fig. 2a, 3,), a logic zero level is set at its output (Fig. 2 g), which launches a chain of series-connected waiting x multivibrators May 1st. Depending on the required multiplication factor, the number of waiting multivibrators in the chain is set to either equal to the multiplication factor or less than one. Suppose that the pulse frequency of the input pulses needs to be multiplied by five, the chain in this case should consist of five waiting multivibrators.

The pulse length of the logic zero from the outputs of the waiting multivibrators 1-5 with a multiplication factor of five is set to one tenth of the input pulses, and the duration of the pulse from the output of the multivibrating standby 5 can be set to more than one tenth, but not exceeding one fifth input pulses. Thus, when a logical unit level impulse arrives at the input bus 10 at the outputs of the waiting multivibrators 1-5, a logic zero level pulses are formed, the duration of which is one-tenth of the input pulses, at / this impulse of each subsequent /

the multivibrator is delayed by one tenth of the period of the input pulses relative to the output pulse of the previous waiting multivibrator. The leading edge of a logical zero pulse from the output of a standby multivibrator 5 triggers trigger 7 (Fig. 2 3, moment ii), while its output sets the level of logic zero, and the output of element 9 inequality - the level of logical unit (Fig. 2) the first input of it (on bus 10) at this moment maintains the level of the logical unit (Fig. 2a

At the moment of termination of the input pulse of positive polarity (Fig. 2a, moment tj), the output of the inequality element 9 establishes the level of logical zero (Fig. 2 g), since at its inputs at this moment there are levels of logical zero. A logical zero pulse from the output of the inequality element 9 re-launches a chain of serially connected waiting multivibrators 1-5, the outputs of which generate logical zero pulses (Fig. 2 b, c, d, e, e, time interval t2-l4) - the leading edge of the pulse the logical zero from the output of the waiting multivibrator 5 (Fig. 2 e, time tj) again triggers trigger 7, while the output of the inequality element 9 is set to a high level of the logical unit (Fig. 2 g).

Thus, by the end of the period of the input pulses, the frequency multiplier assumes the initial state for starting the chain of waiting multivibrators 1-5 on the leading edge of the input pulse of the level of the logical unit.

During the period of the input pulse; ow at the output of the element b –I – NOT (figure 2 interval-tg), pulses of the level of a logical unit are formed, and the duration of two of them is equal to one fifth of the period of the pulse, and the middle of these pulses coincides with or with the falling edge of the input pulse of the logical unity level (Fig. 2 and mMoHTati, t4b on the scroll 11 during the input signal period in this case four pulses of the level of the logical unit are formed, and at the output of the unequality element 8, on the bus 12 a pulse signal is formed with ck azhnostyu equal to two, the frequency of which sequencers five times higher than the repetition frequency of the input pulses.

Claims (2)

If the pulse frequency of the input pulses needs to be multiplied by six, then the duration of the output pulses of the waiting multivibrators 1-5 is set to one twelfth of the input signal period. In this case, a pulse signal with a duty cycle equal to two is generated at the output of element 6 AND-NI, the frequency of which six times exceeds the frequency of the pulse of the input pulses, and at the output of the logic element 9 of unequalities during the period of the input signal five pulses of the logical unit are formed. . Thus, at an odd multiplication factor (m 3, 5, 7, etc.), an output pulse signal with a duty cycle of two is formed at the output of the unequal element 8 (output bus 12), with an even multiplication factor (m 2 4, b, etc.) - at the output of the NAND element (output bus 11). In this first case, on bus 11, and in the second case, on bus 12, a pulse signal is generated, obtained by multiplying the frequency of the input pulses by a multiplication factor of (m -1). (The duty cycle is not equal to two). With odd multiplication factors in order to reduce by one the number of pending multivibrators, the inputs of element 6 I-NOT can be connected to the outputs of the pending multivibrators, with even order numbers. For example, with a multiplication factor equal to five, the inputs of element 6 I-NOT can be connected to the outputs of the waiting multivibrator 2 and 4. In addition, the chain of series-connected waiting multivibrators 1-5 with any multiplication factors can be replaced by a multiphase pulse shaper, The outputs with odd {or even) sequence numbers of which are connected to the inputs of element 6 AND –NE. This device, in addition to multiplying the pulse frequency of the input pulses, can be used to form the front and back edges of the input pulse of a logical unit of pulses with a specified number of pulses in a packet. At the same time, since the initial phase of the pulses in the packet is rigidly fixed to the fronts of the input pulse, the harmonics of the spectrum of the output signal do not depend on the filling frequency of the packet. When it changes, only the movement of the spectral envelope of the radio pulse along the frequency axis occurs. In this case, the spectral lines of the output signal do not change their position on the frequency axis, remaining located at points multiples of the first harmonic of the spectrum of the input signal, and the spectral line located on the frequency axis closest to the frequency of the pulse in the packet has the maximum amplitude . Synchronizing the output oscillations of the multiplier twice during the period of the input signal leads to a decrease in the level of the spectral components of the output signal of the frequencies on the axis from the main spectral component by a distance equal to the odd harmonics of the input signal (1, 3, 5, etc.), which facilitates subsequent filtering, output. Claims of the invention A pulse frequency multiplier comprising N; (where N is 1, 2, 3, ..., N) series-connected stand-by multivibrators, characterized in that, in order to increase the phase stability of the output signal, NOT, two logical elements of inequality and trigger, the counting input of which is connected to the output of the N-th multivibrator, the input of the first multivibrator is connected to the output of the first non-unequal element, one input of which is connected to the trigger output, and the other its input is connected the first input of the second element and nonequivalence with input bus element inputs of an AND-NO element are connected to outputs of odd multivibrator, an output of AND-NO element is connected to a second input of the second element nonequivalence. Sources of information taken into account in the examination 1. The author's certificate of the USSR 317083, cl. G About F7 / 52, 1971. 2. Patent of the GDR No. 95875, cl. H 03 B 19/10, published. 1978 (prototype). t, 42 3 " FIG. FIG. g