SU564634A1 - Multiplying-dividing device - Google Patents

Description

(54) MULTIPLE-UNIFIED DEVICE

one

FIELD: computer engineering.

A multiply-depoped device is known that contains counters, a trigger, keys, and a group of coincidence circuits ij. This device is difficult and has low speed.

The closest in technical essence to the invention is a device comprising a first counter, the input of which through the first element I is connected to the first input of the device, the bitwise outputs of the first counter are connected to the first group of inputs of the block of elements I, the second group of inputs of which is connected to the inverse - outputs of the second counter, and the output of the block of elements And through the first trigger is connected to the input of the second element And, the output of the second counter through the second trigger connected to the first inputs of the first and third elements And, watts swarm input of the second flip-flop connected to the first input of the fourth AND gate, the second inputs of the third and fourth AND elements podklvchv s respectively to the second and third

device input and elements And 2j. However, this device is difficult and has low speed.

The aim of the invention is to simplify the device and increase its speed.

The goal is achieved by the introduction of two elements OR a delay element, an input connected via the second AND element to the output of the first trigger, and an output through peJ) You and the OR element to the first input of the second OR element, the second input of which The first element is connected to the fourth input of the device. The output of the second element OR is connected to the input of the second counter. The second input of the first element OR is connected to the output of the fourth element I.

The drawing shows a block diagram of the device.

The device contains counters 1 and 2, elements AND 3-7, elements OR 8 and 9, triggers 1О and llj c.J delay cement 12 and block 13 elements I. The device operates as follows: Input 14-17 receives input values f, f and f d 1 Tjj, where N "is the conversion factor of counters 1 and 2. In the initial state, counters 1 and 2 are in the zero state, elements AND 4.6 and 7 are open, and elements And 3 are closed. Through the open elements AND 4 7, the inputs of counters 1 and 2 receive pulses with frequencies f and fj, respectively. When the counter overflows with 1, the signal from its output flips to one state the trigger 10, and the signal from the output of the last And 4 7 elements are closed, and the And 3 element opens the c. The time Tl required for overfilling of the counter 1 is determined by the expression T / L 2. During this time, the counter 2 receives the NUMBER of pulses equal to Through the open element AND 3 a signal of duration T arrives at the input of the element 5. And opens it. Through the temporarily opened T. element AND 5, pulses with a frequency f are fed to the input of the element OR 9 and then to the input of the counter 1. To the second input of the element OR 9, from the output of the element 6 and through the delay element 12, impulses with a frequency of f are received. The frequency of the pulses at the output of the element ILR1 9 is equal to

9-.6

{3} with frequency

Impulses

 2 exit

block 13 elements AND arrive at a single input trigger 11. The average frequency f of the pulse following at the output of block 13 elements AND, determined by the frequency of the pulses f a i supplied from the output of the element OR 9 through the element OR 8 to the input of the counter 1, and the number N

2 written in counter 2 is equal to

 J9n

(4) .3 - N

m

In the initial state, the AND 6 element is open, and the pulses from the output of the OR 9 element arrive through the open element AND 6 to the input of the delay element 12 and

Claims (2)

1. USSR author's certificate No. 1435524, Q 06 F 7/38, 10.23.1972. 2. USSR author's certificate No. 404173, H 03 B 19 / OO, 06/28/1968.