SU556502A1 - Random access memory with blocking of defective storage elements - Google Patents

Description

"And connected respectively to the inputs of the control unit and the block for forwarding faulty bit groups, the counter output is connected to one of the inputs of the coding block, and the counter inputs are connected to the outputs of the second OR element and the control unit, respectively.

The drawing shows a block diagram of the proposed random access memory with blocking faulty storage elements.

The device contains address register 1, address decoder 2, main drive 3, word register 4, additional drive 5 containing reserve groups of bits, control unit 6, block 7 of forwarding faulty groups of bits made, for example, in the form of an associative memory block, the first control unit 8, for example, performing parity checking by groups of bits, the first elements “AND 9, the first 10 and second 11 elements“ OR, the counter 12, the third element “OR 13, the second elements“ And 14 and 15, the coding unit 16 and the second block 17 of the control.

The inputs of the register 1 address are connected to the pin 18 of the address, and the outputs are connected to the inputs of block 7 and through the decoder 2 to the drive 3, the outputs of which are connected to the inputs of register 4. The outputs of the latter are connected to the inputs of drives 3 and 5, block 8 of the control, as well as to the output buses 19. The inputs of the second control block 17 are connected to the outputs of block 7, and the output to the input of control block 6 and one of the inputs of block 7, the other inputs of which are connected to the outputs of the first control block 8, the inputs of the OR 10 element of the coding block 16 and one of the inputs of the first elements And 9, the outputs of which are connected to the inputs of the element “OR 11, the outputs of block 7 are connected to other inputs of the elements“ AND 9 and to the inputs of the element “Pi LI 13, the outputs of elements 10, 11 and 13 through the elements“ And 14 and 15 are connected respectively to the inputs of the control unit 6 and one of the inputs of the unit 7, the output of the counter 12 is connected to one of the inputs of the coding unit 16, and its input - to the output of the element "OR I.

The device works as follows.

The address code on the bus 18 enters the register 1, then after the application of the circulation signal (write or read) to the control unit 6, a cycle of writing or reading information begins. Consider first the read cycle. When contacting a serviceable address, the device operates as usual: the word selected from the decoder 2 from accumulator 3 goes to register 4 and then to output buses 19 and inputs of block 8. In this case, there is no information from the outputs of block 7 and outputs of block 8, and the control unit 6 generates a signal for the end of the read cycle.

If a readout fails or is damaged in the storage elements, leading to distortion of information in the word (one or several bits), block 8 will detect an error and give a signal to the control unit 6, which will begin to execute the program that detects , a failure or failure has occurred (for example, multiple readings on the same

address). When a fault is detected, block 6 issues a signal about this, in-service information at the seams 19, and a signal for the end of the call. However, if a failure has occurred, block 6 issues a signal according to which the work on this program cannot continue and it is necessary either to re-execute a part of the program from a certain part of it, or to re-add a certain part of the program to the device from the outside.

When a failure is detected, the control unit 6 also generates signals that store information on registers 1 and 4, writes the code of the faulty address to the indication part of block 7 and the address of the corresponding

the reserve group of bits of the additional accumulator 5 into the information part of block 7.

Let us consider in more detail how the formation of the code of the address of the backup group

bits of additional storage 5 and the optimal filling of its volume. Drive 5 contains several (in the drawing three) reserve groups of bits, therefore the address of any reserve group of bits must

consist of the address of a word in accumulator 5 and an indication of which groups of bits of the given word replace the failed one. The address of the word is specified by the counter 12 in binary code, and the information indicating the replacement spare group of bits is generated by the control unit 8 determining the operability of each group of bits and entered into the bits of the information part of block 7. The number of such bits in block 7 is equal to the number of groups of bits in the word additional storage 5.

In order for the additional accumulator 5 to be optimally filled, it is necessary that the backup groups of bits be connected to work with the main accumulator according to such a law that would allow the use of all the reserve groups of bits of the additional accumulator 5, but

It would not be necessary to periodically re-arrange the information placed in block 7. The objectives of optimal filling are the elements “AND 9, 14 and 15 and“ OR 10, And and 13, as well as a special program, realizable

the control unit 6 and the counter 12. With the same purpose, when entering into the indicative part of block 7 the code of the faulty address, the address of the word of the additional drive, which

set by counter 12.

All new information entry in block 7 is performed according to the following program.

First, in the indicative part of block 7, the code of the main storage address is masked, and reading occurs at the address (starting from zero) issued by the counter 12. In this case, the contents of the bits are analyzed, indicating that the bit groups are faulty. If the information recorded earlier in these bits coincides with the information at the outputs of block 8, then at this address of accumulator 5 it is impossible to use a backup group and under the action of signals from the element "OR 11 and block 6" is added "1 and again produced reading from the block 7 bits of signs of malfunction, and so on until the output of the element "OR 11" and there is no match signal. Then block 6 will begin to enter information from register 1 and counter 12 into the indicative part and information from block 8 and counter 12 into the information part of block 7. After the next address of the reserve group of bits is written, block 6 outputs a process end signal. The device is again ready to perform its functions.

When reading from the device, the address code received on register 1 is checked for its presence in block 7 (this masks the address code from counter 12) and if it coincides, block 7 outputs the corresponding code of the backup group (or groups) of bits in the additional drive From which, in parallel with the working groups of bits of the main drive, register 4 will receive readable information. If it is intact, then block 6 generates a signal for the end of the read operation and information on the tires 19. However, if reading the information from the main accumulator 3 and the reserve groups of bits again fails, then there are two possible reasons: either a failure has occurred. the group of bits of the word of the main accumulator 3, or the storage element in the backup group used in this operation failed.

In the first case, which will be detected by the signal from the element AND 15 (due to the absence of a signal at the output of the element OR), the control unit 6 generates a signal which completely releases the cell in block 7 (i.e. will erase the information in its attribute and informational part x), which has just been addressed. After 4eio, the program described above, the entry of non-addressing information into block 7, i.e., the counter 12, controlled by block 6 and the signals from the OR element, will start the serial address (pachina from zero), will find the free cell in additional drive 5 and will issue its address to block 7. Thus, any faulty device address code is in the indicative part of block 7 only in one

her cell It is easy to see that when such a program is executed when recording information in block 7, the volume of additional storage device 5 is used most optimally.

and there is no need to periodically recompose the contents of block 7.

In the event of a failure of the storage element in the reserve group of bits, the element “And 15 again gives a signal about the need for the released cell 7 of the block 7 from the forwarding information recorded in it and block 6 begins the cleaning (erasing) of this cell. However, in this case, not all information recorded in

This cell, and only the code of the malfunctioning address of the accumulator 3, written in the indicative part of block 7. All the rest of the information (i.e., the entire information part and the address code of the additional tip 5, recorded in the indicative part of the cell of block 7) remain unchanged, as their erasing is prohibited by the signal at the output of the element "AND i4, arising from the failure of the storage element in the reserve ground of the bits.

The information stored in this way in the cell of block 7 during the queue of recording information in block 7 will prohibit the use of the failed backup discharge ground. Then block 6 enova begins the cycle of entry

the information is redirected to block 7. Thus, the proposed device allows automatic blocking of faulty groups of bits that occur during operation both in the PARTICULAR tip 3, and

and additional storage 5.

Failures of the gripping elements can occur in the block 7 itself of forwarding unauthorized groups of bits, and these failures will not be detected by block 8. Therefore, it is advisable to use block 7 with self-control, in which unauthorized cells automatically block. This is done as follows. When recording information in block 7 block

16, its parity code is formed, which is also entered into block 7. When reading information from block 7, it is checked for parity by block 17, whose error signal during a special fault

The cells of block 7 (after establishing the presence of a failure) are signaled prohibiting access to this cell. After this, block 6 starts the cycle again of recording information and sending it to a new cell of block 7 according to the program described above.

Claims (1)

Invention Formula Random access memory with blocking faulty memory elements containing the address register connected through the address code to the main drive, the word register connected to the first control unit, the main and additional drives, the forwarding of faulty sockets bits, connected to the address register, the word register, the additional drive and counter, block control, encoding unit, elements “AND and“ OR, second control unit, differently in order to increase the reliability of the device, the inputs of the second control unit are connected to the output of the forwarding unit groups defective bits, and the output - to the input of the control unit and one of the inputs of block groups divert defective bits, the other inputs of which are connected to the outputs of the first control unit, inputs of said first element "OR of the coding block and one of the inputs of the first elements “AND, whose outputs are connected to the inputs of the second element“ OR, the outputs of the block for forwarding faulty groups of bits are connected to other inputs of the nerve elements “AND and the inputs of the third element“ OR, the outputs of the elements “OR through the second elements "And connected respectively to the inputs of the control unit and the block for forwarding faulty groups of bits, the output of the counter is connected to one of the inputs of the coding block, and the input of the counter is connected to the output of the second" OR.