SU546111A1 - Counter register-adder - Google Patents

Description

pa, ./- the input of which is connected to the bus is complicated, and the 5-input to the sychtang pin, the code generation block contains a 5-flip-flop, the 5-input of which is connected to the prohibitory input liHBepCHOMV and the first input of the code generation block, and -in The move is to the output of the prohibit element, and the output of the 5-flip-flop is connected to the input of the accumulator module two, the second input of which is connected to the second input of the code generation unit, and the output to the output of the code generation unit, the direct input of the prohibition element, is connected with the third input of the code generation unit.

In the drawing, a functional diagram of the meter is presented.

The counter contains an I-bit register / shift towards the low-order bit, code generation block 2, consisting of the element 5 "prohibition, / 5-trigger 4 and adder 5 modulo two, adder 6 modulo two, RStrigger 7 , counting bus 8, sdvngayush, bus 9, installation bus 10, bus // "complex, e / 2" subtraction.

The counting width 5 of the counter is connected to the input 2- / of the code generation unit 2, the output of the lower order is connected to the input 2-2 of the block 2 of the code input. The output of the adder 6 modulo two is connected to the input 2-5 of the code generation block 2. The output of the code generation unit 2 is connected to the inforg,; the corresponding input of the register. The high-order output of the register / is connected to one of the inputs of the adder 6 modulo two, the second input of which is connected to the output of “1 flip-flop 7, impl, your control of the account mode. The two inputs of the aforementioned trigger are connected to the control of the Shiami "addition // and" subtraction 12 devices.

Modulo two output of the adder 5 is the output of the code generation unit 2, while one of the inputs of the adder 5 is the input 2-2 of the code generation unit 2. The information input of the prohibit element 3 is input 2-3 of the code generation unit 2, and the prohibition, Ayush, and input of the prohibition element 3 connected to the input of the 5-flip-flop 4 is the input of the 2- / unit of the code generation. The output of the element 3 "prohibition is connected to the input of the thrunger 4, the output of which is connected to the second input of the adder 5 but module two.

In addition mode, trigger 7 is preset to position "O. Thus, in the course of operation, the information input of element 3 "prohibition through modulator 2 modulator 2" will receive the direct values of the code written to the high register / shift value. Let the initial register code O ... 00. The counting pulse via bus 8 enters the trigger input 4, set, and put it at position “I, which in turn provides inverse feedback to regnetter / through modulator 5. Synchronously with a counting pulse on a clock 9 input clock register input, a clock pulse is fed, providing a high-order register of a logical "1" register (reading the register backward link / via adder 5 modulo two). The appearance of a single signal on the high-order output of the register / causes the switching of trigger 4 in the state "O (after the end of the counting pulse of the locking

element 3 "prohibition). The feedback of the register / through the adder 5 modulo two becomes direct, n when applying the following i-1 shift pulses on bus 9 during all bits of the register /, with the exception of the younger one,

zeros will be taken up. Thus, after the first cycle of counting in the register /, the code O ... 01 is set. the value of the logical "O. After the arrival of the second shift pulse, the value of the logical "1" is written to the most significant bit, which causes the switching of the trigger 4 to the state "O", therefore the register feedback / through the sum of the modulator 5 becomes direct. After the arrival of the subsequent ft-2 shift pulses on bus 9 in register 7, the code O ... 010 is set. As you can see from the example, in the patch of each counting cycle trigger 4, which controls the feedback of register Y through adder 5, mod two , is set to “1”, and its setting to the “O” position occurs when the first unit at the output of the high register register / in the process of operation occurs. It follows that after the third counting cycle in the register, the O ... 011 code will be recorded, after the fourth cycle, the O ... 0100 code, etc. Thus, 32 each summation cycle occurs by increasing the contents of the Y register by one, t . e. binary unit count.

When working in the subtraction mode, the trigger 7 is set to the position "1, so during the operation, the input RS of the thrunger 4- through the element 3" prohibition and adder 6 but the module two will receive the inverted values of the code written in

high bit register. This means that in the state "On", the trigger 4 will be switched in the counting process by the first zero written to the most significant bit of the register /. Otherwise, the operation of the circuit does not differ from the previous mode. Thus, if the initial state of the register is 1, O ... 00, then after the first counting cycle, the state of the register / will be 1 ... 11, after the second counting cycle I ... 110, after the third 1 ... 101 and etc., i.e.

for each counting cycle, the Mi: e register 1 is reduced by one, which corresponds to the work in the “subtraction. The inclusion of element 3 "prohibition in the device due to the need for reliable installation of the trigger 4 in the state" 1 s

the arrival of a counting pulse on the counting bus 9, even if there is a “1 in the most senior de register register (when operating in the“ addition ”mode) or logical“ On (when operating in the “subtraction mode”).

Formula and 3 o b e e e c i

Claims (2)

1. The tiaia counter-sugmatmator counter, which contains the lower-order shift register, the code generation unit and the input counting, shift, and installation buses connected to the first input of the code generation unit, clock input and installation shift register, respectively, the second input The code generation unit is connected to the low-order output of the shift register, and the output is connected to the information input of the shift register, which is that, in order to expand its functionality, an adder is entered into it modulo two and 5-flip-flop, the output of the higher bit of the shift register through the modulo two adder is connected to the third the input of the code generation unit, the second input of the modulo two adder is connected to the output of a / 5 flip-flop, the input of which is connected to the addition bus, and the S input is connected to the pin subtraction. 2. A counting instrument according to Claim 1, clause 1; and with the fact that the code block contains a / 5 trigger. 5in which is connected to the inverse input of the element "prohibition and to the first input of the block code generation, Y-input - to the output of the element "prohibition, and the output of the / 5-flip-flop is connected to the input of the adder and its module two, the second input of which is connected to the second input of the code-forming unit, and the output - to the output of the code-generating unit, direct input the element “lock” is connected to the third input of the form code block. Sources of information taken into account in the examination of the invention. . Auth. swith No. 226983, H 03 25/00. 1968 2. Bukreev I.I. and others. “Digital Electrochemical Devices of Digital Devices, P1.,“ Owls. ) adio, 1973. p. 174 (prototype).