SU542328A1 - Digital frequency discriminator - Google Patents

Description

one

The invention relates to a pulse technique.

A digital frequency discriminator is known, comprising a crystal oscillator, six multivibrators, inverters, two pulse drivers, AND gates, shifting a register, an integrator, a level detector, counters, and mismatch logic circuits ll.

Also known is a digital frequency discriminator containing a driver, the inputs of which are connected to clock and discriminating frequency sources, and the output is connected to one of the inputs of logic elements 11, the second inputs of which are connected by the corresponding inputs of a reversible counter, the decoder whose inputs are connected to the outputs of a reversible counter, the input the installation of which is connected to the clock source, and the output is connected to one of the RS trigger inputs, a resistor whose outputs are connected to the multichannel inputs switch, and the write input connected to the output of the decoder.

The purpose of the invention is to simplify the discriminator.

The goal is achieved by introducing an additional decoder into the proposed discriminator and a delay element, the inputs of the additional decoder are connected to the corresponding outputs of the reversible counter, and its output is connected to the second input ds of the trigger, the control input of the multi-channel switch is connected through the delay element to the input register setting and connected to a clock source.

The drawing shows a block diagram of the proposed discriminator.

Claims (1)

The discriminator contains a shaper 1, an HAZ-trigger 2, logic elements 3 and 4, a reversible counter 5, decoders 6 and 7, a delay element 8, a register 9 and a multichannel switch 10. At the inputs 11, the clock frequency signals are given, and the input 12 is a signal discriminated frequency The output signals are taken from the outputs of the multichannel switch 1O. The discriminator works as follows. At a low level of the clock frequency, the passage of pulses of the discriminated frequency through the shaper 1 is blocked. At the same time, the RS flip-flop 2 is set to a state where a high level appears at the Q output and a low level at the Q output. . A circuit of passing pulses of a discriminated frequency to the summing input of the reversing counter 5 through element 3 is prepared. The passage of pulses of a discriminated frequency to the subtracting input of the reversing counter 5 through the element 4 is blocked. In addition, when the clock frequency is low, a reversible counter 5 is installed, once the information is read by the switch 10c of the register 9, and after a certain time the register is set, Discrit; the Inator is ready for operation. When a high level of clock frequencies appears, a pulse of discriminated frequency of flow through the summing input of the reversing counter 5, and when the maximum number is written in the counter (corresponding to the number of its bits), a low level appears at the output of the decryptor 6. In this case, the GAZ-trigger 2 is switched, and the pulses of the frequency being discriminated are passed to the subtracting input of the reversing counter 5. As soon as the number of pulses received at the subtracting input is compared with the number of pulses received at the summing input (i.e., O), a low level appears at the output of desphragrator 7, switching the RS-flip-flop 2, and pulses of the discriminated frequency pass to the summing input. Such alternate operation of the up / down counter 5 for summation and subtraction continues for the entire measurement. The output desh pulses (| of the googr 7, appearing every 2–2 pulses of the discriminated frequency (where a is the number of bits of the reversible counter 5), are fed to the input of the register 9). At the end of the measurement time, i.e. a low clock frequency, the number recorded in register 9 is read out and excited by one of the channels of the switch 10. After a certain time, register 9 is set and the digital frequency discriminator operation is repeated. Due to the alternate summation and subtraction in a reversible counter The number of its bits, which leads to a simplification of the discriminator. Formula of the invention A digital frequency discriminator containing a driver, the inputs of which are connected to clock and discriminating frequency sources, and the output connected to one of the inputs of logical elements And, the second inputs of which are connected to the corresponding reverse inputs the counter, the decyfrater, the inputs of which are connected to the outputs of the reversible counter, the installation input of which is connected to the clock source, and the output connected to one of the inputs R, S-flip-flop, a resistor whose outputs are connected to the inputs of a multichannel switch, and a write input connected to the output of the decoder, characterized in that, in order to simplify it, an additional decoder and a delay element are inserted, and the inputs of the additional decoder are connected to the corresponding outputs reversible counter, and its output is connected to the second input of the RS flip-flop, the control input of the multichannel switch is connected via a delay element to the register setup inputs and connected to the clock source Nala. Sources of information taken into account in the examination: 1. US patent N 3418586, cl. 329-104, 12.24.68.