SU531286A1 - Controlled frequency divider - Google Patents

Description

one

The invention relates to a pulse technique.

Devices are known for dividing a pulse frequency with a goat-controlled conversion factor l, 2J.

The first of the known devices for recalculating pulses from yppaBL e aIm by the counting factor comprises a primary and secondary counter, a gate on the input, a switching trigger associated with this gate, elements of coincidence, and an OR element.

The second of the known devices is more perfect, is selected as a prototype and contains two parallel-connected counters with a variable conversion factor, two AND elements, an ILI element and a delay that is included at the input of the first counter.

However, this frequency divider has limited functionality, due to the difficulty of obtaining large division factors.

The aim of the invention is to expand the range of the division factors. For this, an additional AND element and an additional OR element connected in series and connected between the input of the first and the output of the second counter are introduced into the proposed frequency divider, the output of the second counter through one of the AND elements is also connected to the first input of the OR element. To the other input of which the output of the first counter is directly connected.

The drawing shows an electrical structure of the described frequency divider.

The device contains two counters 1 and 2 with a variable conversion factor, delay line 3, three elements AND 4, 5, 6, two elements OR 7, 8, terminal 9 of the source of input signals, terminals 10, 11, 12 of the sources of control signals.

Claims (2)

The device works as follows. High-frequency pulses are received at device terminal 9. The input signal is directly fed to the input of counter 2 and through the delay line 3, element 4 and element 7 or 7 at the input of counter 1. When the control signals to terminals 10 and 12 of counter 1 and 2 are turned on simultaneously in parallel, the total division factor is determined according to the formula: When alternating control signals (terminals 1O and 12), counters 1 and 2 operate alternately. The total division factor is calculated by the formula: CMS where - A is the number of pulses received at the input of counter 1; B - the number of pulses received at the input of the counter 2. When a control signal is applied to terminal 11, the counters 1 and 2 are connected in series, which allows to obtain large division factors. In this case, the division factor is calculated by the formula:. In addition, the additional elements of AND 5 and the element OR 7 allow alternating the switching on of counter 1 and 2, as well as parallel and sequential switching on to alternate with the operation of 6 of the counters, which also leads to the expansion of the functionality of the controlled frequency divider as a whole. Claims of the invention A controlled frequency divider comprising two parallel connected counters with variable conversion factors, two AND elements, an OR element and a delay line included at the input of the first counter, characterized in that in order to expand the range of the division factors, an additional element is introduced into it. And an additional element OR connected in series and connected between the input of the first and the output of the second counter, the output of the second counter through one of the elements And is also connected to the first input at the OR element, to the other input of which the output of the first counter is directly connected. Sources of information taken into account in the examination: 1. USSR author's certificate number 354578 cl. H 03 K 23/00, 1972 2, US Patent No. 367398 cl. 328-48, 1972, (prototype). Jjjlf-