SU525243A1 - Logarithmic analog-to-digital converter - Google Patents

Description

I

} The present invention relates to the field of radio engineering and can be used in the development of instruments using a digital measurement of the relative attenuation between two different levels of the signal under study.

A device containing a comparator is known, through an integrator connected to the output of the first key, the control input jcoTOporo and the control input of the integrator: connected to the outputs of the control unit, another output of which is connected to the control input of the second key, through which the source of the reference voltage is connected to the reference the input of the Hcomparator, the output of which through the control unit podi / pochen to the control input of the element M-OR,,; another INPUT of the last connection with the output of the generator of counting pulses, and the output connected to the input of the counter , I output; which is connected to one of the inputs of the control unit | A disadvantage of the known device is that in a number of cases it is necessary to measure relative attenuation between any two

By the signal levels, In this case, npKMejrni is a well-known transducer, you need a HIJOBOCTH measurement of attenuation at two points, and, iv, we calculate the required reduction by calculation. Separate measurement and scaling increase the total measurement time for one: Parameters,: which reduces the drivers (: labor.

Claims (1)

 The aim of the invention is to increase, speed and expand the functionality of the device. To achieve this goal, the counter is made rovering and a coincidence element, an inverter, an OR element, a twoK5 trigger,, a trigger with a counting input, a prefixer and an encoder, the input of which is connected to the source of the Control Code signal, the second to the first the output is the decryption of the ator, the third with the output of the reversing account. The output of the encoder is connected to one of the reversible inputs: the Counter, the other input of which is connected to the output of the control unit, the throtin is the OR element of the output of the deciding unit / g, the second output of the decoder, click- control and the input of the first RB of the trigger the second input of which is connected to the trigger pulse source, the inverse output to one of the decoder inputs, the main output to the first input of the coincidence element, the second input of which is connected to one of the counter outputs, the third input with the trigger input with the counting input and through the inverter - with the output of the generator of counting pulses and one of the inputs of the decoder, the other two inputs of which are connected to the outputs of a trigger with a counting input. The setup input of the latter is connected to the output of the coincidence element and the first input of the second TR 5 flip-flop, the second input of which is connected to the third output of the decoder, the inverse output to one of the inputs of the control unit, and the main output to one of the inputs of the decoder programming. To do this, a trigger signal shaping unit, an additional short-circuit trigger, an additional matching element, a driver and a one-shot, through which the source of start-up pulses is connected to the input of the control unit, are introduced into the analog-to-digital converter. This device is connected to the output of an additional S flip-flop, one input of which is connected through the trigger generation unit to the output of the signal source allowing the code to be set, and the second input through the driver is connected to the output of the additional matching element The input of the encoder, FIG. 1, shows a functional circuit of a log-analog-to-digital converter. In FIGS. 2 and 3, signal timing diagrams at various points in the converter. Log-analog-to-digital converter contains key 1, inverter 2, comparator 3, control unit 4, reversible counter 5, key 6, counting pulse generator, 7, AND-OR element 8, decoder 9, inverter 10, match element 11, RS trigger 12, a trigger with a counting input 13, an encoder 14, an OR 15 circuit, a trigger 16, a single vibrator 17, a match element 18, a trigger signal generation unit 19, a trigger 20, and a forwarder 21, the Converter operates as follows. The analog Ug under study is fed to the key 1 input. At the initial moment, all the keys are closed before the impuls-USASI trigger arrives and the voltage of the integrator 2 output is zero. The trigger pulse (Fig 2, a) is fed to the installation input IZ of the trigger 16 and translates one of its outputs into logical ones. This voltage (FIG. 2 b) is applied to one of the inputs of the coincidence element 11, the mentioned trigger pulse acts on the b OK} T1e.phen 4, which opens the key 1 and the AND-OR 8 scheme. As a result, the BbJxoAiioe the integrator 2 E knocks to change (Figs. 2, c), and imgulsya from the generator of counting pulses 7 through the element AND-OR 8 arrive at the input of the reversible counter 5 (Figs. 2, d). After accumulating counts. of the given h of the Silent. Ups, on his B, on the way of Vl5gat0 sigkal logical I (Fig, 2, d). which is connected to one of the inputs of the owl element a. 11, at the joint of the I-blades at its inputs (on one - from the trigger 16, on the other from the counting 5, on the third - from the counting generator 7 7 through the inverter U) at the output of the Wits logical (FIG. - 2, e), which is fed to the installation input of the trigger with the counting input 13 and translates it into a state of logical l through the main output. The same signal is supplied to the setup input and S of the trigger 12 and switches its main output to the logical 1 state (Fig. 2, i). The signal from the inverse output RS of the transceiver 12 is fed to the control unit 4 and through it closes the key 1, In the integrator 2, it can be xrp; Gychchovan, for example, an operational amplifier with F;: 3icoK: fflvi input resistance. This will allow us to memorize the output voltage of the Hirrei rator and for a certain time interval after the key 1 has been closed (Fig. 2, c). When the output of the element coincides with 11 in TC the logical O (Fig. 2, a), then pulses are applied to the inputs of the decoder 9: from the main and inverse outputs jfpHiTepa 13 (phage, 2, g, h), from the main output of the R9 trigger 12 (Fig 2, i), from the output of the generator of counting pulses 7, and one; “p the inverter Yu (fkg 2, k, n} and the other - from the inverse output of the trigger .16 (Fig. 2, m), the Combined mentioned pulses arrive on three three-input elements of the match IS –NE, which form the decoder 9, 8 as a result of the output of the distributor 9, the signal of the logical O (Fig. 2, n), which is Without the element OR 15, it translates into zero matching with echik 5, through the control unit 4 switch over / over the counter 5 to subtraction, as well as nepeao.eaiT S trigger 16 to composes logical 1; io w.1f (output (FIG “2, m). Following emt. (FIG. 2, n), at the other output of the decoder 9, a pulse of logical O is applied, which affects the encoder 14. As a result, the counter 5 is in zero state, the code determined by the external control signal Uyj, p is written, and the pulse from the third output of the decoder 9 (FIG. 2, p) translates into CL3 trigger 12 to the log state about the main output (FIG. 2, and), thus closing the two elements of coincidence to the identifier 9. The signal from the inverse trigger 12 (FIG. 2, m), followed by a falling front on the jTipaBneaiia 4 block, determines the moment of opening the AND-OR 3 element, the key of the discharge circuit the capacitor C of the integrator 2; After this, the countable pulses through the element OR-AND 8 are fed to the input of the counter 5, and the said capacitor is split by the exponential law (FIG. 2, c) to the reference level Vy, Mp It is a comparator 3, the output of which scans through the engraving unit 4 closes the element and-OR 8 and the arrival of inputs to the input of counter 5 ceases. Capacitor C is discharged for some time, after which, with the help of an additional key connected in parallel, it is completely discharged. At the same time, key 6 is closed. As a result, the output code of counter 5 is equal to the difference between the set code and the one obtained in 1) the result of the measurements. If the set cooTBGTCTByfjT code is one of any captured measured voltage, the result of the measurement expresses the attenuation in dB of any value of the measured voltage relative to the preselected one. To ensure internal programming, the code to be set can be equal to the one of the values of the output code of the counter 3. The output code of the counter after the measurement progress is saved until the next protection pulse (Fig. 3a), and the output (setting the code signal C, Fig, 3, b) goes to the block of the formation of the start signal 19 and through it sets the KS trigger 2 O to the logical 3 state (FIG. 3, B). The impulse sa IJjiAn (Fig. 3, a) triggers one-time ITj whose output signal (FKG 3, d) nocrjiiaea to one input of the coincidence element i 8 (AND-NOT type) and to the other its input post output signal H of the trigger 20 (FIG. 3, c). As a result of the coincidence at the output of co-ownership 18, a signal is formed (FIG. 3, i), razpayupushchy; remember 1. you are up- x-; j.: XHorc: changing the code of the checker 5 using the codec 1 and aio of device 14 The same signal, with its falling edge through shaper 21, translates the output level of a 2 O trigger (Fig. 3, c) into a logical O state, thereby prohibiting the distance the latest arrival of one-shot pulses 17 to the encoder 14. During the subsequent measurement cycle, a new code value is pre-recorded in counter 5 with the pulse postulated (Fig. 2, p) from the decoder 9, Measurement result attenuation in dB of the measured value of cz4 на relative earlier in value. This selection is made by memorizing the output code of the counter B, corresponding to a certain value of 13 bx using an encoder 14. Claim 1, A logarithmic analog-to-digital converter containing a comparator, via HHTerpaTopj connected to the output of the first caliper, whose control input and integrator control input connected to the outputs of the control unit, another output of which is connected to the control to the main input of the second switch, through which the source of the reference voltage is connected to the reference input of the comparator Pa, the output of which through the control unit is connected to the control element AND-OR, the other input of the latter is connected to the output of the generator of counting pulses, and the output is connected to the input of a counter, the output of which is connected to one of the inputs of the control unit, characterized in that To increase speed and enhance functionality, the counter is reversible and a match element, an inverter, an OR element, a dual-trigger trigger, a trigger with a counting input, a decoder, and a coder are entered. control signal source, the second with the first outputs of the decoder, the third with the output of the reversible counter, and the output of the encoder connected to one of the inputs of the reversing counter, the other input of which is connected to the output of the control unit, the third through the OR element to the output of the block 11.11.11 and the second output of the decoder, the input of the control unit and the input of the first RS of the second input of which is connected to the source of the trigger pulses, the inverse output to one of the inputs of the decoder, the main output to the first input ementa coincidence, the second input of which is connected with one of counter outputs, the input tretvy - with a trigger input with a counting input n through an inverter - with a counting pulse generator output and one of the scrambler-j inputs of the rator, the other two inputs of which are connected to the trigger outputs with counting input 5, the setup input of the latter is connected to the output of the coincidence element and first entry BTOporoRS trigger; the second input of which is connected to the third output of the decryptor,; inverse output - to one the inputs of the control unit, and the main output - to one of the inputs of the decoder, 2, the transducer according to claim 1, characterized in that, in order to provide internal programming, in; 15 | a trigger block forming unit, an additional Q5 trigger, an additional matching element, a driver and a one-shot through which the source of the trigger pulses is connected to the input of the control unit and one of the inputs of the additional matching element, the other input of which is connected to the output of the additional trigger, one input It is connected via the block of formation of the trigger signals with the output of the signal source that allows the code to be set, and the second input through the driver is connected to the output of the additional overlaps and entry encoder. VjffnQ uraz  Output SHLSH lpl fus.2  f t 8 t / e.3