SU507900A1 - Memory device with blocking defective storage cells - Google Patents

Description

(54) STORAGE DEVICE WITH BLOCKING MALFUNCTION STORAGE CELLS

the tether 9, the elements And, the first and second elements of T-1LI 13 and 14, and the polynomial element And; : 15. The drive 8 can be implemented both in the form of an associative memory device, and in the form of a half-address random access memory device.

The inputs of address register 1 and the address inputs of accumulator 8 are connected to address code 16. The outputs of address register 1 are connected via address decoder 2 to accumulator 3, the outputs of which are connected to inputs of register 4. Registers 4 are connected to inputs 6 and 6 output information buses 17. Information outlets

18block 6 are connected to informational inputs of accumulator 8 and inputs of decoder 7, the outputs of which are connected to inputs of register 4. Informational outputs of accumulator 8 are connected to inputs of additional decoder 9, and outputs of the latter are connected to inputs of register 4. I will give the outputs of the decoders 7 and 9 connected to the inputs of the elements AND 1O-12, the outputs of which are connected to the inputs of the first element 13, and its output is connected to the control input of the drive 8. The inputs of the second element OR 14 are connected to the information outputs of the drive 8, its output is connected to one input of an additional element MIS, the other input of which is connected to the output

19 of block 6, and the output is connected to the control input of the accumulator 8. A multiple (double) error signal is output via the bus 2O.

The device works as follows.

The address code is simultaneously applied to the address register 1 and the address register. accumulator inputs 8. When accessing a serviceable address, the device operates as usual: the word selected from the address decoder 2 from drive 3 is fed to register 4, and then to output slots 17 and inputs of block 6. In this case, the correction information on the decoder outputs 7 and 9 is missing.

When a polling or damage occurs in the memory cell, resulting in the distortion of 1 information in one word, block 6 provides correction information which, after the decoder 7 has passed, corrects information B in register 4. At the same time, the information K11 is corrected from block 6, the posthui: -: T la input of accumulator 8 and gui ciir to a single error message on bus 20 from block 6 is entered into it. At the output of the decoder 9, there is no Kaka or information (all zeros). If quotation 8 is an associative and paging device, then in the indicative part of it, the address of the word in which the error is detected is also memorized; in the case of operational storage

device corrective information is recorded at the address corresponding to the address code on the bus 16. With a secondary call at the same address, two cases are possible depending on what was

fixed before this - crash or memory cell failure. Let the failure be corrected. Then, when the secondary address is sent to the same address (in the absence of new failures or failures), the same faulty cell again gives incorrect information to register 4. However, the drive 8 issues corrective information recorded in it at this address and corrects the information in register

. Since the signal of debris 9 arrives at register 4 no later than Word from accumulator 3, block 6 does not detect an error, there are no signals at the output of the decoder 7 and it arrives at the output bus 17; good information If a malfunction or fault appears in another case on the left (i.e., the second error), it is corrected by block 6, while the first is controlled by Drive 8.

The information from block 6 about the second error is not entered into the drive 8 in order not to spoil the information stored in it about the error.

So, the device has the ability to correct two errors in a word at the same time (if they are successively followed), while the Hamming code can fix only one. When a third error occurs or at the same time and more error

side, this device can not correct them and issues a multiple error signal on bus 20. Suppose that the error from a failure was originally corrected to this address, then during the secondary circulation

At this address (in the absence of other new errors in this word), register 4 of accumulator 3 will receive correct information, but it is immediately distorted in the category in which the first

times, since the inventory information about this rank was 3b.peesana at this address B. drive 8. In addition, this bl.) to 6 will also issue corrections)) u / oi1 1o pi-

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this at the outputs of the decoders 7 and 9, relative to shchs to this bit, there will be the same conditions that go to one of the elements AND 10,11,12 and further to the element OR 13, the signal from which clears the correction information on this address. Thus, the drive 8 is freed from the layer; tea information failures and stores it, with only information about failures. If ; after the first correction of information from the failure of the second access to this address, another error occurs, then unit 6 responds as in the case of a multiple (double) error and generates a signal via bus 20.

So, this device allows you to automatically correct up to two errors in a word at the same time. If it is necessary to increase the correction capacity of the device, it is necessary to introduce several drives (such as drive 8) with their decoders, providing a sequential recording of the correction information in them from block 6, and also it is necessary to construct an appropriate scheme to erase random information from failures.

In the case of applying the proposed

devices as part of the operating system

 The mining device shown in the drawing block diagram must be supplemented

appropriate recording schemes; length

The words in block 6 should be increased by a single digit to store information recorded during an online recording into a corrupted word bit.

Claims (1)

Invention Formula A memory device with blocking of defective memory cells containing an address block connected to a drive, a register whose outputs are connected to a coding unit connected to a decoder, elements AND | 1OR, about tl and h and e, so that, in order to improve the reliability of the device, it contains an additional; a new decoder and an additional accumulator, the address inputs of which are connected; To the Inputs of the address block, the information inputs to the outputs of the coding block, and the information outputs to the inputs of the additional decoder, the outputs of which are connected to register moves, the outputs of the decoders are connected to the inputs of the AND elements, the outputs of which through the first element OR are connected to one control input an additional accumulator, whose information outputs through the second element OR are connected to one input of an additional element AND, the other input of which is connected to the output of the coding block, and the output; connect with another control input of the additional storage device.