SU482901A1 - Binary counter with a constant number of units in bits - Google Patents

Description

valves 16-22, as well as schemes “OR 23-29, delay line 30 and valve 31. The device operates as follows. The number of different “n-bit” states in a code W of n is C, where C is the number of combinations.

So for the counter in code 3 and 6 there will be the following sequence of states 000111100011

001011100101

001101100110

001110101001

010011101010

010101101100

010110110001

011001110010

011010110100

011100111000,

defined by the following recalculation rules in the W code from n: the counting is performed according to the rules of binary counting, starting from the first digit; in the case of the formation of end-to-end transfer through K bits, where I am 2, 3, ..., W, / C-1, the unit must be recorded on the K-1 of the first bit places.

Pulse-Potential Valves 10, And, 31 pass a pulse when recording in the triggers of the counter zero. Gates 12, 13, 14, 17, and 18 transmit a pulse when writing to the unit's meter triggers. The latch 9 of the first non-zero bit transmits a pulse arriving at the input of the counter via the bus 8 until the first bit in which the unit is written. Depending on the state of the counter, this input pulse can pass through one of the valves 2, 13 or 14 and, after passing the valve, enter the counter input of the corresponding counter trigger, which will start with this bit, recalculate the number in the binary code . The corrector of the first W-1 flip-flops 15 consists of gates 16-18, 22 that record the unit to the first trigger and gates 19-21 that record the unit to the first and second meter triggers.

If the first unit in the rth trigger of the counter 1, and in the trigger r + 1 is written zero, then all the equalizer 15 will be closed.

The control pulse generated from the input pulse counter passes through one of the gates 16-18, 22 equalizer if and only if there are 1 units in the i-th and t + 1-m trigger triggers of the counter, and / + 2 in the trigger recorded zero. In this case, according to the rules of binary counting, when a next counting pulse is applied to the counter input, a continuous transfer will occur through 2 bits. The impulse from the output of one of the valves 16-18, 22, through the scheme “OR 23 will go on the record in the first trigger of the counter. The control pulse will pass through one

from the gates 19-21 of the corrector, if and only if in any three neighboring triggers of the counter units are recorded. In this case, when the next counting pulse is fed to the input of the counter, a through transfer will occur through 3 bits. The impulse from the output of one of the gates 19-21 through the scheme “OR 23 is applied to the record in the first two trigger triggers.

A delay line 30 is needed to ensure that triggers are triggered at one-pulse start. Valve 31 serves to set the zero state of the counter in the event of overflow.

Subject invention

A binary counter with a constant number W of units in n bits, containing n counting triggers, the unit output of each of which is connected to the counting input of a neighboring higher trigger trigger, the latch of the first nonzero bit on 2 (n-W) - 1 gates and the corrector of the first W-1 flip-flops from W-1 rows of IDs containing p-2, p-3, p-W gates each, with zero outputs of the first p-W-: flip-flops connected to the first inputs of the p-W-1 gates of the first clamps nonzero discharge, the second input of each of which, except for the valve of the first discharge, is connected to the output the valve of the previous discharge, the single outputs of the first p-W flip-flops are connected to the first inputs of the remaining p-W valves of the first non-zero discharge lock, the second input of each of which, with the exception of the first-discharge valve, is connected to the output of the previous discharge valve connected to zero output of the trigger, and the output is connected to the input of the trigger of its discharge, the second inputs of the first discharge valves of the latch of the first non-zero discharge are connected to the input bus, the single inputs of 2, 3, ..., n-1th of the triggers are connected to one of inputs p-2 The first ply offset of the first W-1 triggers, the second inputs of which are connected to the outputs of the latching valves of the first non-zero discharge connected to the single outputs of the previous discharge triggers and to the outputs of the first-corrector gates of the previous discharge that are connected to the first inputs of the gates the next row of the corrector, the second inputs of the valves of the corrector of the next row are connected to the outputs of the valves of the corrector of the subsequent discharge of the previous row, and the outputs of the valves of the corrector of each row are connected a calculating inputs of flip-flops from the first to / n-th, where m number of rows, characterized in that, to reduce the number of gates, the output gate connected to the single output of the first flip-flop, is connected to the counting input of the first flip-flop.