SU482880A1 - Pulse Length Converter - Google Patents

Description

The invention relates to the field of computer technology and can be used in analog computers, and in automatic devices for monitoring the performance of electronic systems using time-to-moment transformation. The known Pulse width converter, the contents of the control unit, the double irreversible counter, the comparison circuit, the register, and the stable frequency generator do not provide a constant for the conversion coefficient for slow changes in the frequency of the input sequence. The purpose of this invention is to provide a constant transform coefficient for slow changes in the frequency of the input sequence. The goal is achieved by introducing a frequency divider into the converter, an additional impulse counter and a valve group, the output of the stable frequency generator through a frequency divider, an additional pulse counter and a valve group connected to the register. FIG. 1 shows the structural scheme of the proposed converter; in fig. 2- timing diagrams, and the operation of the proposed converter. The proposed converter of the duration of pulses contains a block of 1 controls, the state n1, s from the circuit 2 of a single short pulse, the circuit “AND 3, the circuit“ OR 4, the second circuit “AND 5 and Two and the sigher 6 and 7, the binary non-reversible counter 8 NMpulsov, circuit 9 comparisons, a stable frequency generator 10, a frequency divider 11, an additional counter of 12 pulses, a valve group 13, a register 14 and a delay element 15. The input of the pulse duration converter is connected to the input of a single short-pulse circuit, to the input of the inverter 7 and to one of the control inputs of the AND 3 circuit. The output of the inverter 7 is connected to one of the control inputs of the second And 5 circuit, the output of which, like the output The "AND 3, OR 4" circuit is connected to the counting input of a binary non-reversible counter 8. The cells of the binary non-reversible counter 8 are connected to the inputs of the comparison circuit 9, the output of which is the transmitter's output, through the inverter 6 is connected to the second The "3 and 5" input terminals of the stable frequency generator are connected directly to the pulse input of the "3" circuit and a frequency divider 11 with an adjustable division factor 1 (.- (where K is the pulse width conversion factor) to the second pulse input schemes "And 5 and to the counting input

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11 solar counter 12 pulses. Each cell of the additional counter 12 pulses is connected to the corresponding gates of the ven- tal, 13 group 13 connected to 11 numerical moves of the register 14, and the outputs of which are to the BTOpi iM inputs of the eranium circuit. In addition, the output of the single short pulse circuit is connected to the reset input of the binary non-reversible counter 8, to the control inputs of the valves of the valve group 13 and through the delay element 15 to the reset input of the additional counter 12 pymuls.

The proposed pulse duration converter works as follows.

Rectangular impulses (Fig. 2) with variable duration / in and with the magneowei value of Yernod T arrive at the converter input. The leading edge of the input pulse through the single short impulse circuit sets the binary non-reversible counter 8 to the initial zero state, acting on the valve group 13 opens valves and produces a non-cutting code from the additional counter 12 pulses to the register 14, which, through the delay element 15, goes to the reset circuit of the additional counter 12 pulses and sets it o to iul state. By entering the “I 3” circuit, the input impulse permits the passage of an impulse frequency F from the output of a stable frequency generator through the circuit “OR 4 a binary non-reversible counter

482880

8. At the end of the input pulse, 1i-n pertor 7 gives permission for the passage of the frequency F2 from the output of divider 11 through the “AND 5 and OR 4” circuits to the input of the binary and internal counter 8. Frequency A pass 1 to 2 on the binary non-reversible counter 8 for some time / i, until the incremental counter code 8 coincides with the code recorded in register 14. At the same time, a thermal output is obtained at the output of the comparison circuit 9. which, through inverter 6, prohibits the passage of frequencies FI and P2 to the input of a binary non-reversible counter 8 and is saved at the output of the pulse duration converter / par of the arrival of its next pulse and setting the binary non-reversing counter 8 to the zero state of a single short pulse 2.

Subject invention

A pulse width converter containing a control unit, a binary non-reversible counter, a comparison circuit, a register, and a stable frequency generator, characterized in that, in order to ensure the constant of the conversion coefficient of prn slow changes in the frequency of the input sequence, a frequency divider is inserted in it, an additional counter of puls and a valve group, the output of the stable frequency generator being connected via a frequency divider, an additional counter of imiuls and a valve group connected to the register.

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FIG. 2