SU546107A1 - Analog Relay Converter - Google Patents

Description

6, output trigger 7, generator 8 time intervals, circuit 9 for filling a pulse of a frequency pulse generator /.,., selector 10 of a back edge of a generator pulse, selector 11 of a leading edge of a generator pulse, first. intermediate trigger J2, prohibition 13, second intermediate trigger 14.

The converter works in the following way.

When the input signal reaches the trigger threshold level or the release threshold level, the corresponding latch outputs a pulse signal either to the input S of the output 5-flip-flop or to the third input of the gating circuit (input 5 of the first intermediate 5-flip-flop).

In the initial state, when the pulse at the third input is absent, the etrobing scheme passes the signal “initial from the output of the rear edge selector pulse to the generator of time and intervalals” through the “inhibit” circuit and the second intermediate 5thrigger to the output R of the output 5-thru | Gger. At the same time, the signal from the output of the selector of the leading edge of the pulse (the third output of the synchronization circuit) is fed to the second input of the testing circuit and sets the first intermediate 5-trigger to the state where the signal is absent at the inhibitory input of the circuit.

When a release threshold is released at the output of the latch (third input of the stubbing), the signal is in the form of a logical "1", the latter is simultaneously fed to the input S of the first intermediate S-flip-flop and to the input R of the second intermediate RS-trigger. The first trigger, when triggered, creates at the requesting input of the circuit “prohibition of the signal in the form of a high level and, thus, it prohibits the transmission of the signal“ initial to the second intermediate 5-trigger. The second intermediate S-trigger, when triggered, creates at the input R of the output / 5-flip-flop (output of the testing circuit) a signal in the form of a low level (logical "O), i.e., the output 5-flip-flop does not change in this state.

The converter can be divided into four most characteristic modes:

1st release | M, when the input signal is either absent or it is less than the level of the release threshold (initial state);

The 2nd mode, when the input signal rises to the level of the release threshold when rising from a zero value, then exceeds it, but remains lower than the operating threshold;

3-nd mode, when the input signal exceeds the threshold level;

The 4th mode, when the input signal decreases from the maximum value to the value of the release threshold level, but does not reach it.

When a pulse-frequency modulator is applied to the input of a direct current signal at the corresponding input of the "P" circuit, a signal appears in the form of pulses with a frequency dependent on the magnitude of the signal. Simultaneously from the output of the generator of time intervals to the second input of the scheme

The back edge selector and the pulse generator of the time intervals are given pulses calibrated in duration. At the same time, from the output of the circuit "P" to the input of the counter, a signal is given in the form of pulse pulses, the following frequency and the duration of which are determined, respectively, by the follow-up frequency and the pulse duration of the time interval generator, and the number of pulses of the packet pulse is determined by the frequency / d. on the size of the input signal (operation of the converter in the first mode at the outputs of the latch of the threshold of operation and latch of the threshold

releasing signals are in the form of a low level (logical "O), so the signal" initial as logical "1 from the output of the selector of the falling edge of impulses of the time interval generator through the" prohibition "circuit goes to input S of the second intermediate 5 flip-flop that triggers and gives a signal in the form of a logical "1 to the input R of the main 5-flip-flop, which corresponds to an output signal in the form of a level.

When the input signal rises at the output of the latch of the release threshold level, a pulse signal appears in the form of a logical "1, which prohibits the passage of

the " initial, but does not change the state of the second intermediate 5-flip-flop and the output / 5-flip-flop.

With a further increase in the input signal there are pulsed signals

both at the output of the latch of the threshold of the threshold, and at the output of the latch of the release threshold level, and at the output of the latch of the level of the trigger threshold. In this case, the signal at the output of the first intermediate 7 5-flip-flop remains in the form of a logical "1", the signal at the output of the second intermediate 5-flip-flop in the form of a logical "O, and the signal from the output of the latch of the trigger threshold in the form of a logical" b changes

output state of 5-trilitera such that a high level appears at its output.

When the input signal drops to the value of the output signal

the latch of the trigger threshold takes the logical value "O, but since both inputs of the output / 5 flip-flop have a logical" O, its state does not change. Thus, despite

input equality and identity

states, the output signal has opposite states, since the input signal is in the hysteresis region.

Claims (2)

1. Analog-relay converter for converting, for example, voltage or frequency into a relay signal containing a trigger level trigger, characterized in that, in order to increase the conversion accuracy, a pulse-frequency modulator is inputted to it, the input of which is connected to the source input signal, timing circuit, counter, latching release level lock, gating circuit and output 7 5-flip-flop, and the output of the frequency-pulse modulator is connected to the input of the timing circuit, one of the outputs of which It is connected to the counter input of the counter, the second is connected to the reset of the counter and to the first input of the gating circuit, the third is connected to the second input of the gating circuit, the latch inputs of the trigger threshold and latch release threshold are connected to the corresponding counter bits. the output of the latching level of the trigger threshold is connected to the input S of the output 5-flip-flop, and the output of the fixture; the threshold level of the release threshold is connected to the third input of the gating circuit, the output of which is connected to the input R of the output / 5-flip-flop. 2. The converter according to claim 1, characterized in that the gating circuit comprises a first intermediate / 5 flip-flop, a "prohibitory" circuit and a second intermediate S-trigger, the input S of the first intermediate S-flip-flop being connected to the input R of the second intermediate 5-flip-flop and a third the input of the gating circuit and the output with the prohibition input of the prohibition circuit, the information input of which is connected to the first input of the gating circuit, and the output of which is connected to the input S of the second intermediate 7 5 flip-flop, the output of which is connected to the output of the gating circuit. Source of information taken into account in the examination: 1, Patent of Great Britain No. 1313917, 04/18/73, cl. NRT. S g lR 7