SU474003A1 - Device for multiplying pulse frequency - Google Patents

Description

which is connected with the output of the adder 4 and with the input of the second frequency divider 10 connected by the output with the second input of the control unit.

In the initial state, the storage register 3 and frequency dividers 9, 10 are in the "zero states", the coincidence circuits 8, 11 are closed. The pulses from the generator 2 of the reference frequency are fed to the first input of the period selection and control unit I.

The operation of the device starts from the moment it arrives at the third input of the control unit I of the first input pulse corresponding to the beginning of the period 7 of the input signal /. The control unit 1 from the first output generates a signal through the OR7 circuit and the delay line b to the first inputs of the matching circuit 5. The number recorded in the storage register 3 is transferred in the reverse code to the adder 4. The zero state of the storage register 3 corresponds to that recorded in its number 0. The number of bits in the memory register and adder - p.

All triggers are in the "zero state".

During the transfer, a number is written in adder 4, which corresponds to the "single state of all triggers of the adder. The signal from the first output of the control unit 1 also arrives at the second input of the coincidence circuit 11 and opens it, arriving at the waste bus of the first and second frequency dividers 9, 10, confirms their "zero state."

The control unit 1 begins to pass through the pulses of frequency / o from the generator 2 of the reference frequency. These pulses come from the second output of the control unit 1 to the input of the adder 4. The first frequency pulse / o will overflow the adder. In the event of overflow, the adder outputs an impulse from the output, which through the open coincidence circuit 11 goes to the output of the device. The pulse from the output of the adder 4 is also fed to the input of the second frequency divider 10 and through the OR 7 circuit and the delay line b to the pulse inputs of the coincidence circuit 5 for the next transfer of the number in the reverse code from the storage register 3 to the adder 4. Ta: K as in the storage register O remains unchanged, then the frequency at the output of the adder will be equal to fo. When the number of pulses K from the output of the adder 4 is equal to the multiplication factor of the device and the division factor of the second frequency divider 10, the second divider will receive a pulse to the second input of the control unit 1, which closes the coincidence circuit II from the first output and the output opens the coincidence circuit 8. The frequency pulses fo start to flow through the coincidence circuit 8 to the input of the first frequency divider 9, which has a division factor K. From the output of the first divider

frequency frequency - fed to the input of the lock

dividing register 3.

From the output of the adder 4, the pulses continue to flow, but they do not pass to the output; since the coincidence circuit 11 is closed, the output pulses from the second frequency divider 10

the control unit 1 is not affected until the next input pulse of the multiplied frequency, j, arrives. . Upon receipt of the second input pulse, the blocking potential from the third output of the block

Control 1 closes the coincidence circuit 8. The arrival of pulses in the storage register 3 is terminated.

From the first output of the control unit 1, a signal will come through the "OR 7, line

delays 6 to the pulse inputs of the matching circuits 5, the signal will be sent to the second input of the matching circuit 11 and to the fault inputs of the first and second frequency dividers 9, 10. Frequency dividers 9, 10 will be set to the "zero state, and the matching circuit 11 will open for passing pulses from the output of the adder 4 to the output of the device. From the storage register 3, the number is transferred in reverse code to adder 4.

Thus, during the time T. between two input pulses / (equal to the period of the input signal), K pulses were received by the output of the device through the coincidence circuit I1. The time during which the output pulses passed through the AND matching circuit is equal to TO-K, where Go is the period of the output signal of the reference frequency generator. The time during which the frequency pulses / o were received through the coincidence circuit 8 and the first divider

frequency 9 on memory register 3, equal to

G, -Go - / (.

The number of pulses received in the storage register 3 is determined by the expression:

T x -Tr-K

(one)

- N +,

Current

where N is the number of pulses recorded in the memory register; DL is a fractional part of the quotient.

After the arrival of the second input pulse at the input of the control unit 1 from the storage register 3, the number written in it is transferred in the return code to the adder 4. As a result, the number 2-2-L will appear in the adder; the initial number that was in adder 4 before the transfer does not affect the transfer result.

To overflow the adder 4 with the frequency / o (period Go) entering it, it is necessary () pulses. When the adder overflows, a pulse goes through the coincidence circuit 11 to the output of the device, to the second frequency divider 10 and to the coincidence circuit 5 for the next transfer from the storage register 3 of the number N in the return code. Frequency at the output of the adder and at the output

devices is ---, and the period is N + 1

TO (N + 1). The adder in the device performs the role of a controlled frequency divider.

When the output of the adder 4 K pulses the second frequency divider 10 will issue a signal to the second input of the control unit 1, which closes the output matching circuit 11 and opens the matching circuit 8 before the arrival of the next input pulse.

From the formula (1)

T. - To-K

 L + DL

Current

determine the period T of the input frequency

T,

-

Current

T

 L + 1 + AiV; G., 7o / C (-V + 1+ AL)

Go k

 To-K (N +) + To - / (AA.

Let us find the transit time of the K output pulses with a period ToCV + l). It is equal: To {N +) - K. Let us compare the period of the input signal Г Го / C (V + 1) + Го / CAjV with the time K of the output pulses T,. K (N + l).

These time intervals differ from each other by Go-TS-AL, where AL is a fractional value, the minimum value of which is O, and the maximum tends to 1.

Depending on the value of the AL, the output pulses can be distributed strictly evenly within the period of the input signal at AL 0 (an ideal case of multiplication) or with an error at. Go () is the period of output pulses; Go / S-AL - the total error from the non-multiplicity of periods of the input and output signals.

When AL is close to 1, the maximum is the total error due to non-multiplicity about

T, -K.

If, the maximum total error due to non-multiplicity is equal to the quantization step (the period of the output signal Tu); when the maximum total error of non-multiplicity is less than the quantization step.

The total error from non-multiplicity, equal to the quantization step, is permissible. When measuring the output frequency fy, it can increase the frequency meter readings by one low-order bit.

When measuring the output frequency, the occurrence of the maximum error is unlikely, since the AL / should be close to 1 and the measurement ends at a certain point in the second half of the input signal period.

In order to fulfill the condition when the occurrence of a maximum error due to non-multiplicity equal to quantization is possible, it is necessary that, and therefore, the maximum output frequency from multiplying the input frequency by / C times be less than the frequency / o generator of the reference frequency.

fo

/.

TO

where is the output frequency of the device.

The coincidence circuit 8 opens at the time of the PG -7о-Л (ЛЧ1) Го - / (- АЛ. Since G - КАЛ ГО / С, then the memory register

3 pulses from the first frequency divider 9 are not received. To receive a single pulse e frequency divider 9, it is necessary for the coincidence circuit 8 to be open for the time To-K. In the steady state mode, the number recorded in

the memory register remains constant. For different input frequencies, it is different.

After the arrival of the third input pulse, the sequence of operation of the device nodes is repeated. Thus, after the arrival of the second input frequency pulse / s, the device begins to operate in steady state. The transient after applying the first input pulse is one period of the input signal. After the arrival of the first input pulse, K output pulses arrived at the output, but they were unevenly located within period G. input signal. With the arrival of the second input pulse output Wits K

output pulses uniformly located within the period G ,, the input signal. The operation diagram of the device after the arrival of the first input pulse is shown in FIG. 2, where are shown:

a) input frequency f;

b) output frequency / y;

c) output pulses from the second frequency divider 10;

d) output pulses from the first frequency divider 9.

In the steady state mode, for each input pulse, control unit 1 receives an impulse from the output of the second frequency divider 10.

Consider the operation of the device when the input frequency changes during the multiplication time.

The first case is a decrease in the input frequency (increase in the period). The subsequent input impulse entered through the weft time T T. The time at which the coincidence scheme opens 8. will be equal to: G ,. -Go K (N + l).

The number of pulses that have passed to memory register 3 is determined by the expression

G.u-Go-K (.U-I)

  F + F,

(2) Go-D

55 where F is the number of pulses received in the memory register; Af is a fractional part.

Determine the magnitude of G. from the formula (2)

 - () f + Af;

Current

t,

.: N + F + I + APa-k

T To-K (N + F + l) + To-K- & F. (3)

In the storage register 3 at the initial steady state, the number L was written. As a result of the change in the period of the input signal to the memory register 3, F pulses are appended. The new number in the memory register is (L + /). When transferring the number (N + 1) in the reverse code from the storage register 3 in the adder 4, the number 2 -L-F-1 will be written. The adder begins to divide the frequency / o by L + O- + 1, therefore, the period of the output signal will be Go (N + F + l). The boom during which the output pulses arrive, will make TQ- (N + F +) comparing it with expression (3), we see that it differs from the new period T by 7 ° / C D, which corresponds to the error of non-multiplicity of the input and output periods signals.

It is the established mode. The non-transition process in this case constitutes one period of the input signal, during which K, the output pulses are unevenly located within the period of the input signal.

The device operation diagram for this case is shown in FIG. 3, where:

a) input frequency / y;

b) output frequency /;

c) output pulses from the second frequency divider 10;

d) output pulses from the first frequency divider 9.

Consider the operation of the device with increasing input frequency (reducing the period).

When reducing the period of the input frequency, the order of the input to the control unit 1 of the pulses of the input frequency I and the pulses from the output of the second frequency divider 10 varies. One after another, two pulses of the input frequency arrive at the input of the control unit 1, the pulse from the second frequency divider 10 between them does not have time to pass. When the second input pulse arrives, the control unit 1 generates a signal from the fourth output, which resets the storage register 3 to the "zero position" and, entering through the "ILR1 7" circuit and the delay line 6 in the coincidence circuit 5, rewrites the number in the reverse code from the memory register "O, corresponding to its" zero position, in adder 4. At the output of adder 4, the frequency / o is set. The second frequency divider 10 is forcedly filled and sends the first pulse to the second input of the control unit 1, which does not affect the device. The output matching circuit 11 remains open, the matching circuit 8 is closed. The next bundle of K pulses will arrive at the device output. When the K th pulse arrives, the second frequency divider 10 will give a second pulse to the second input of the control unit 1.

The control unit 1 closes the output AND matching circuit and opens the matching circuit 8. The storage register 3 from the first frequency divider 9 will start to receive pulses before the next input frequency pulse J arrives. control unit 1 may still receive several pulses from the output of the second frequency divider before the arrival of the input frequency pulse, they will not have any effect. When the input frequency pulse arrives, the control unit 1 closes the coincidence circuit 8, transfers

storing register 3, the number in the reverse code to adder 4, resets the first and second dividers to the "bullet position" and opens the output valve 11. Next, the already known operations are repeated. The t / C passage of pulses to the output of the device enters the impulse from the output of the second frequency divider 10 pa control unit 1, which closes the coincidence circuit 11 and opens the coincidence circuit 8. The memory register 3 begins to receive pulses until the input frequency pulse arrives at the input control unit 1. Thereafter, the steady state begins.

In the considered case, the time of the transition process occupied three periods of the input signal. During the transition process, for each input impulse, the output / s of the output pulses were distributed, but they were not equal to the number within the periods of the input pulses.

The operation diagram of the considered variant is depicted in FIG. 4, where:

a) input frequency /;

b) output frequency / y;

c) output pulses from the second frequency divider 10;

d) output pulses from the first frequency divider S.

The output of the transition process is given below.

We assume that in the steady state at an arbitrary input frequency f. In the memory register 3 is written the number C. The period of the output frequency in this case, Tu To (C + 1).

Input frequency period

T. To-K (C + {) + To.K-AS

where D is the multiplication factor.

Frequency increased (period decreased) n times.

„, Ta-K (C + 1) + To-K AS

The period of the input frequency should be

C + 1

, (four)

During the first modified period T

yy

input signal will be output imp

pulses. After the arrival of the first input pulse by the frequency measurement, the output will go to

D

/ simpuls and another bundle from K impulses

owls All these pulses come at a frequency / o (Go period), since the number 2 -1 is recorded in adder 4.

The time interval for the arrival of pulses is

4- + K} G, (2Kf

7-0 (Go - / ((2-In the remaining time interval between the 5th first and second input pulses, pulses will be sent to the memory register 3 through the first frequency divider. This time interval equals TO K. (C + 1) + Go K LS jt / f) -. п, jlo-J (Z--. Expression (5) will be a positive value, taking into account the following. The input frequency can dramatically change to the maximum. Accepting the maximum error from the input and output frequency times quantization step, we have K, but since, as always, therefore, expression (5) is a positive quantity. (s) -yo-l: -ds g. i -7o.X {2C + 1 + DC To-K (The number of pulses transmitted to memory register 3 is equal to. „. () 2 + -L-. and "C + 1 + DC-2fi + i C + 1 + DC Cpp In the adder will transfer the number with + 1 + m: -2 / 1 + 1 9 pj ± i L; zr 2 - C + 1 + DC-3 / г + 1 п After the arrival of the second input pulse of the changed frequency, a bundle of K pulses with a period of “C + 1 + DC-3rt + l 1 o” will pass to the device.

The transit time of these pulses is equal to 60 vanilla pulses, containing a block of selections + 1 + DS-3 / g + 1. The time interval until the next one comes through the coincidence circuits that control the input pulse, during which 65 inputs through the delay line and pulses to memory

register equal to

С + 1 + ДС-З +1

To-K (C +) + To-K-- C

T ft - o / t-r 1

L ..

with + i-ls-Zgi-:

C + 1 + DS

Current

la

С + 14-АС-С-1-АС + Зп-1

 Go

TO

II 3 / 1-1

7 gol - 1 J O A

P

The memory register will receive a device for multiplying the frequency of the track of the period and control connected to the output of the reference frequency generator and the input frequency bus, the adder, the inputs of the rolls 7- () Зп-1 To-К-п п In the memory register will write the numbers + n + c С -C + LS-2rt l-b3 /; - 1 Upon the arrival of the third input pulse in the adder 4, the number St-1-пp + LS C + 1-1-DS C + l + rt-fAC-n is the fractional part, in the adder 4, write the bristles of the expression part. The period of the output pulses is set to G0–, which corresponds to the expression (4), i.e., the period of the output signal is reduced by a factor of as compared to the original one. The established operation mode of the device has come. The transition process involved three periods of the input signal. This device for multiplying the pulse frequency is recommended to be used for multiplying the frequencies of the low and lateral frequency ranges. The range of multiplied frequencies is determined by the speed of the elements used in the device, the subject invention

The "OR" is connected to the output of the adder and to the first and second outputs of the period allocation and control unit, connected to the outputs of the memory register, the output matching circuit, the inputs of which are connected respectively to the output of the adder and the second output of the period allocation and control unit, the fourth output of which is connected to a counting input of an adder, characterized in that, in order to expand the class of the tasks to be solved, a coincidence circuit and two frequency dividers are additionally introduced into it.

f) (

the first of which is connected between the output of the additional matching circuit and the input of the memory register, the input of the second frequency divider is connected to the output of the adder,

and its output is to the third input of the period-allocation and control unit, the second output of which is connected to the input of the zero setting of both frequency dividers, and the third output is connected to the first input of the additional matching circuit, the second input of which is connected to the counting input of the adder.

(Rig.1

III

FIG. four