SU473183A1 - Discrete logic device - Google Patents

Discrete logic device

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Publication number
SU473183A1
SU473183A1 SU1469017A SU1469017A SU473183A1 SU 473183 A1 SU473183 A1 SU 473183A1 SU 1469017 A SU1469017 A SU 1469017A SU 1469017 A SU1469017 A SU 1469017A SU 473183 A1 SU473183 A1 SU 473183A1
Authority
SU
USSR - Soviet Union
Prior art keywords
logic device
discrete logic
amplifier
output
input
Prior art date
Application number
SU1469017A
Other languages
Russian (ru)
Inventor
Ефим Давыдович Зайденберг
Маргарита Дмитриевна Ходырева
Original Assignee
Предприятие П/Я Г-4086
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Предприятие П/Я Г-4086 filed Critical Предприятие П/Я Г-4086
Priority to SU1469017A priority Critical patent/SU473183A1/en
Application granted granted Critical
Publication of SU473183A1 publication Critical patent/SU473183A1/en

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  • Tests Of Electronic Circuits (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Description

(54) ДИСКРЕТНОЕ ЛОГИЧЕСКОЕ УСТРОЙСТВО(54) DISCRETE LOGICAL DEVICE

1-3, а также дополнительных контактов 9 в блоках 2, 3 вы вл ютс .1-3, as well as additional contacts 9 in blocks 2, 3 are detected.

Участок схемы, показанный на фиг. 2, содержит функциональные логические блоки 12, 13 и выходной блок 14. Блок 12 содержит усилитель 15, выход которого подключен к контакту 16. Один из входов схемы «И 17 блока 13 подключен к контакту 18, соединенному дополнительным контактом 19 перемычкой . Вход выходного усилител  20 блока 14 подключен к контакту 21.The circuit portion shown in FIG. 2, contains functional logic blocks 12, 13 and output block 14. Block 12 contains an amplifier 15, the output of which is connected to pin 16. One of the inputs of the circuit “AND 17 of block 13 is connected to pin 18, which is connected by a jumper to additional pin 19. The input of the output amplifier 20 of the unit 14 is connected to pin 21.

В известном устройстве контакты 16, 18 и 21 соединены между собой непосредственно. Дл  вы влени  обрыва контакта 18 необходим тест, при котором единичные сигналы подаютс  одновременно на вход усилител  15 и на все остальные схемы «И 17 (на фиг. 2 показан одии дополнительный вход).In the known device, the contacts 16, 18 and 21 are interconnected directly. In order to detect the breakage of contact 18, a test is needed in which single signals are simultaneously supplied to the input of amplifier 15 and to all other AND 17 circuits (an additional input is shown in Fig. 2).

В предложенном устройстве входна  цепь усилител  20 соединена с выходом усилител  In the proposed device, the input circuit of the amplifier 20 is connected to the output of the amplifier

15 через перемычку 18, 19. При любом тесте, привод щем к по влению нулевого сигнала на входе усилител  15, обрыв контактов 18 и 19 вы вл етс .15 through jumper 18, 19. In any test resulting in the appearance of a zero signal at the input of amplifier 15, the break of contacts 18 and 19 is detected.

Предмет изобретени Subject invention

Дискретное логическое устройство, содержащее функциональные логические блоки, вентильные элементы которых подключены к контактам разъемов, и выходной блок, отличающеес  тем, что, с целью повыщени  контролеспособности устройства, разъемы функциональных логических блоков содержат донолнительные контакты, соединенные перемычками с соответствующими основными контактами, подключенными к вентильным элементам; причем перемычка включена последовательно с функциональными и выходным блоками.A discrete logic device containing functional logic blocks, valve elements of which are connected to the connector pins, and an output unit, characterized in that, in order to increase the device’s operability, the connectors of the functional logic blocks contain additional contacts connected by jumpers to the corresponding main contacts connected to the valve terminals. elements; moreover, the jumper is connected in series with the functional and output blocks.

1717

2020

2i2i

+ ;+;

Фиг 2Fig 2

SU1469017A 1970-07-22 1970-07-22 Discrete logic device SU473183A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SU1469017A SU473183A1 (en) 1970-07-22 1970-07-22 Discrete logic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU1469017A SU473183A1 (en) 1970-07-22 1970-07-22 Discrete logic device

Publications (1)

Publication Number Publication Date
SU473183A1 true SU473183A1 (en) 1975-06-05

Family

ID=20456422

Family Applications (1)

Application Number Title Priority Date Filing Date
SU1469017A SU473183A1 (en) 1970-07-22 1970-07-22 Discrete logic device

Country Status (1)

Country Link
SU (1) SU473183A1 (en)

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