GB1305010A - - Google Patents

Info

Publication number
GB1305010A
GB1305010A GB2323371A GB2323371A GB1305010A GB 1305010 A GB1305010 A GB 1305010A GB 2323371 A GB2323371 A GB 2323371A GB 2323371 A GB2323371 A GB 2323371A GB 1305010 A GB1305010 A GB 1305010A
Authority
GB
United Kingdom
Prior art keywords
level
interconnection metallization
usable cells
terminals
heading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2323371A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1305010A publication Critical patent/GB1305010A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291Oxides or nitrides or carbides, e.g. ceramics, glass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118Masterslice integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

1305010 Integrated circuits HUGHES AIRCRAFT CO 19 April 1971 [5 March 1970] 23233/71 Addition to 1282177 Heading H1K The terminals of selected usable cells in an array of randomly distributed usable cells are connected by first and second levels of interconnection metallization to points on a predetermined master circuit pattern, the terminal relocation technique of Specification 1,282,177 being employed in the first level as necessary. The second (top) level of interconnection metallization is provided with special test terminals connected to and of greater width than the conductive pattern to allow tests to be carried out at predetermined standard locations by (for example) automated probe techniques, before encapsulation of the integrated circuit.
GB2323371A 1968-09-25 1971-04-19 Expired GB1305010A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US76245968A 1968-09-25 1968-09-25
US1686770A 1970-03-05 1970-03-05

Publications (1)

Publication Number Publication Date
GB1305010A true GB1305010A (en) 1973-01-31

Family

ID=26689162

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2323371A Expired GB1305010A (en) 1968-09-25 1971-04-19

Country Status (1)

Country Link
GB (1) GB1305010A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1983004109A1 (en) * 1982-05-17 1983-11-24 Motorola, Inc. Pad for accelerated memory test
US4479088A (en) * 1981-01-16 1984-10-23 Burroughs Corporation Wafer including test lead connected to ground for testing networks thereon
GB2153590A (en) * 1984-02-01 1985-08-21 Ramesh Chandra Varshney Matrix of functional circuits on a semiconductor wafer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4479088A (en) * 1981-01-16 1984-10-23 Burroughs Corporation Wafer including test lead connected to ground for testing networks thereon
WO1983004109A1 (en) * 1982-05-17 1983-11-24 Motorola, Inc. Pad for accelerated memory test
US4465973A (en) * 1982-05-17 1984-08-14 Motorola, Inc. Pad for accelerated memory test
GB2153590A (en) * 1984-02-01 1985-08-21 Ramesh Chandra Varshney Matrix of functional circuits on a semiconductor wafer

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Legal Events

Date Code Title Description
PS Patent sealed
PE20 Patent expired after termination of 20 years