SU454699A1 - Pulse dividing device - Google Patents

Description

one

The invention relates to digital computing and can be used as devices for dividing in digital models and specialized calculators.

Known counting devices for dividing, providing division in cases of

l.,

where A is the dividend, B is the divisor,

a is the base of the number system. Known devices include a counting pulse generator, divider, divisible and residual counters.

However, the execution time of the division by known devices is

  0)

/ ("T

it grows rapidly with growth t because it is proportional to a. This circumstance limits the scope of application of known devices due to poor temporal characteristics.

The aim of the invention is to reduce the fission time.

(It is necessary to reduce the time division to

 + a (/ i-1) 1 j-.

Proportional (t-1), which with increasing t increases much slower than a).

For this, the output of the generator of counting pulses is connected via the first key to the inputs of the dividend, divider and remainder counters, the output of the remainder counter is connected via the second key to the input of the dividing counter divide circuit control circuit, and the output

0 divider counter - to the input of the transfer of the residual counter to zero and the input of the pulse distributor, whose outputs are connected to the bits of the private counter, the output of the counter de. Limo through frequency divider connected to

5 to the locking input of the first key and the unlocking input of the second key, shifting the input of the pulse distributor and to the input of the delay element whose output is connected to the unlocking input of the first key, input

0 converting the remainder counter to zero and the input of the divider counter dividing coefficient control circuit, the second inputs of dividing divider and divider dividing coefficient dividing circuit control circuit are connected to

5 sources of impulses divisible and divisor, respectively.

The drawing shows a block diagram of the device. Pulse dividing device

0 contains counters of divisible 1 and divisor 2

with dividing coefficients set using dividing coefficient control circuits of dividend 3 and divider 4 counters, the first key 5, on one input of which counting pulses of frequency F are received from the generator of counting pulses 6, and on the others - control signals, frequency divider 7, having a division factor., quotient count in with bits 8-1,

8-2. 8-3 8-m., Each of which has

the division factor is equal to a, the remainder counter 9, which is set to zero by signals from the output of divider counter 2. The input of the remainder counter 9 is connected to the output of the first key 5. In addition, the device contains a second key 10 providing the transfer of the residual code from the remainder counter 9 into the control circuit of the division factor of the dividend counter 3, controlled by the signals from the output of frequency divider 7, the pulse distributor And, controlled by the signals from the output of frequency divider 7, providing alternate connection of the output of the counter of cases 2.A bodies entry MSB counter 8-1 private 8, the delay element 12 provides a delay signal output from the frequency divider 7 for a time sufficient to rewrite the residue from residue code counter 9 in the dividing ratio counter control circuit 3 of the dividend.

The output of the delay element 12 is connected to the input of the nerve key 5 and to the input of setting the zero state of the residual counter 9.

The device works as follows.

In the initial state, the inputs of the control circuits of the division factors of the dividend divider and divider 3 and 4 are given the signals characterizing the values of the divisible A and divider B, respectively, and the keys 5 and 10 are set to the "closed" state.

Signal "start set:

- in the dividend and divisor counters 1 and 2, the division factors equal to A and B, respectively;

- residual counter 9 - to zero state;

- distributor of pulses 11 - to the state that provides connection of the output of the counter of the divider 2 to the inputs of the bits of the counter of the private 8;

- the first key 5 to the state of "about to r ryto.

In this case, the pulses of the generator of counting pulses 6 with a frequency F begin to pass through the first key 5 and be counted by counters of the dividend, divider and the remainder 1, 2 and 9.

When pulses are received at the input of a dividend counter 1 Ni aA, the overflow signal from the output of frequency divider 7 closes the first key 5.

Since the input of the counter divider 2 during this time will also receive pulses, then

AL

he overflows ni times and, investigator

but, "1 - the value of the most significant bit of the quotient will be calculated; in bit 8-1 the quotient of the quotient 8

At the same time, each overflow signal of divider counter 2 sets to zero the residual counter 9.

If a

L, aa,

i.e. the division is obtained with the remainder, then after the “i-ro overflow of the divider counter 2, the remainder counter 9 will register the remainder equal to AB

The overflow signal of the divided divisor counter 1 and frequency divider 7, coming from the output of the latter, opens the second key 10 and the residual code AB from the residual counter 9 to the control unit of the division factor of the divisible counter 3 is transmitted; numerically equal to A.

At the same time, this signal enters the pulse distributor AND, which connects the output of the divider 2 counter to the second bit input 8-2 of the quotient private 8 and then, after delay 12, sets the remainder counter 9 to the zero state,

the divider counter 2 sets the division factor to B and opens the first key 5.

In a similar way, all the remaining bits of the quotient will be calculated, after which the signal from the output of the pulse distributor 11 will close the first key 5 and the division will stop.

When performing division with an accuracy of the / nth digit, the first key 5 must pass a number of pulses equal to

A / aA + aAi + aA, -f ...- f. (2)

Considering that, (xA,, ..,

can write

(t-1).

(3)

Then the time of the division

AL 1 + a (from - 1)

f.

(4) F

Comparing (1) and (4), it can be noted that with, for all integer values,

as 1-f-a (m -.

Obviously, with m 1, 2 i, we can show that with m 2, the inequality tz-.ti will also hold.

Obviously, when m 2 the number of pulses transmitted through the first key 5 will be equal to

TV, a (L + RECORDING that Ai aA -5 "i and 0

get at

Consequently,

D, aA - 5 / Zi A (a - 1),

where does that

A + A, aA and -,

Ai

a (A + TO

a Similarly, it can be proved that for m-3 the inequality holds true. Dividing time gain equal to

 - am + a - 1

M f, -f, J (5)

increases rapidly with increasing t.

Subject invention

A pulse counting device containing a divisor counter, a divisor and

The remainder, characterized in that, in order to reduce the division time, the output of the counting pulse generator is connected via the first key to the inputs of the dividend, divider and remainder counters, the output of the remainder counter is connected via the second key to the input of the dividend divider control circuit, and the output of the splitter counter - to the input of the transfer of the zero-balance counter and

the input of the pulse distributor, the outputs of which are connected to the bits of the quotient counter, the output of the divisor counter through the frequency divider is connected to the locking input of the first key and the unlocking input of the second key, the shift input of the pulse distributor and the input of the delay element, the output of which is connected to the unlocking input of the first key, the input of the translation of the balance counter to zero and the input of the control circuit

the division factor of the divider counter, while the second inputs of the control circuit of the division factors of the dividend and divider counters are connected to the sources of the dividend and divider pulses, respectively.

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