SU446052A1 - Buffer storage device - Google Patents

Description

The invention relates to the field of automation and computing and can be used in pulse and digital devices, 5

Buffer memory devices are known to reduce the pulse frequency to a permissible local value (in time) and containing a binary counter, a memory cell, and a control node.

However, the speed of such 5HD devices is limited due to the impossibility of simultaneously acting on the counter of the sequence of input pulses and pulses coming from the output of the control node. The disadvantages of the known devices also include the need for a hard time synchronization of the input and output frequencies, which leads to the logical complexity of the circuits controlling these frequencies.

The proposed device from-.

characterized by the fact that in it the output pulse widths and the input pulse bus are connected to the primary circuits of the first AND circuit and through the delay elements to the first inputs of the second and third circuits AND, respectively. The output of the first AND circuit is connected with the second inputs of the third third AND circuit The output of the second circuit AND is connected to the summing input of the binary counter, and the output of the third circuit AND to the input of the control unit.

This makes it possible to increase the speed of the device.

Diagram of the buffer storage device shownAn the drawing

The device contains an L-bit binary counter I, control node 2, memory element 3, first AND 4 circuit, prohibition signal shaping circuit 5, second AND 6 circuit, third WG 7 circuit, delay elements 8 and 9, bus input mx pulses 10, polling pshnu II and

bus output pulses 12.

The device works in the following way.

The input pulses of the current frequency Lx are fed to the first input of the first circuit AND 4 and through delay element 8 to the first input of the second circuit AND 6. When the input pulse passes through the pulse to the contents of counter I, it increases by one, the pulse polling JP frequency in the event that unit 1 is recorded in memory cell 3, causes the appearance of an output pulse. At the same time, the output pulse is fed to the input of the AND 4 circuit and through the delay element 9 to the first input of the AND 7 circuit. When the Output pulse passes through the AND 7 circuit, using control unit 2, the contents of counter I are reduced by one. The presence of the input pulses of the interrogating frequency and the pulse length of the interrogating frequency with the duration is determined by the AND 4 circuit. and to the input of the control unit 2.

In case the input pulses and output pulses overlap with in time, the output of the AND 4 circuit produces a signal with a duration of 2 G, depending on the coincidence of these pulses. The prohibit signal shaping waveform 5 generates a signal. The prohibition of duration T, if its input has a signal of duration m. At Ti, the prohibition signal circuit 5 is not generated and the input and output frequency signals that overlap during this time are counted at counter I. However, the counter

460524

it is designed in such a way that the joint action of input and output frequency signals over time causes disruptions in its operation. This is easy to accomplish, for example, for counters reacting to the front of input pulses and having rfoccT 2l-T | recovery time.

0 Thus, if the circuit generates a prohibit signal, this means that a write pulse acts at the input of the device and at the same time a pulse of a specific frequency is applied. In this case, the state of the counter ke changes, since the second and third AND schemes do not transmit these pulses. If the prohibit signal is absent, it means that the read and write signals are not

at the same time or that the coincidence time of these signals is shorter than f,

PROMETING ISOBRKEPY

A buffer memory device containing a binary counter whose output through the memory element is connected to the output pulse width, input pulse block, interrogation bar, connection an1) with another memory element input, control node, the output of which is connected to the counter subtracting input, different the fact that, in order to increase the speed of the device, the input pulse bus and output pulse bus are connected to the inputs of the first circuit AND and through the delay element to the primary inputs of the second and third circuits AND, the output of the first circuit, respectively And through the pattern of blocking the prohibition signal is connected to the second inputs of the second and third circuits AND the output of the second AND circuit is connected to the summing input of the binary counter, and the output of the third AND circuit to the input of the control node.

.