SU443474A1 - Amplitude Modulated Pulse Demodulator - Google Patents

Description

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The proposed demodulator relates to the field of radio engineering.

Amplitude-modulated demodulators demodulators are known, which contain two parallel-connected controlled peak detectors, and the amplitude-impulse modulation signal is sent to the information inputs.

The disadvantage of such demodulators is that they create a large amplitude distortion of the useful modulating signal.

The reduction of the amplitude distortion of the useful signal is ensured by the fact that the proposed demodulator contains two peak detectors, a circuit for dividing the sync pulses into even and odd and a circuit for generating an interpolating signal. Moreover, these circuits are connected respectively to the input and output of the face detectors.

On the output of such a demodulator, a voltage is formed that varies during clock periods (polling periods for kaials according to a step-linear law, and this law can be arbitrarily close to a purely linear one. Using a demodulator instead of the known ones that use a step approximation provides a significant decrease in the amplitude distortion of the demodulated signal.

FIG. 1 shows a functional diagram of a demodulator; in fig. 2-time signal diagrams.

The demodulator consists of a delay element 1, Tpnrreipa 2, coincidence circuits 3, 4, controlled peak detectors 5, 6, a diffraction analog multiplying device 7, an emulsion gene 8, a reversing counter 9 and a decoder 10. Figures 11 and 12 denote analog multiplier inputs 7.

Delay element 1 is connected to the counting input of trigger 2, which is connected by single and zero outputs to control inputs, respectively, of joint schemes 3 and

4. The main inputs of these coincidence circuits are connected to the input terminal of SR clock pulses coinciding in time with the pulses of the AIM signal, and the outputs are connected to the control inputs of the corresponding detectors 5 and 6, respectively. The main inputs of the face detectors 5 and 6 are connected to the input terminal of the AIM signal, The outputs are connected to the analog inputs 11 and 12 of the multiplying device 7. The delay element 1, trigger 2 and

Matching schemes 3, 4 together are used to separate the PIM pulses into even and odd. Peak detectors 5 and 6 are designed to expand divided pulses by two clock polling periods.

channels. The generator of 8 impulses is connected to the counting input of the reversible counter 9 connected by a digital input of the multiplying device 7 and the input of the decoder 10. The outputs of the decoder 10 corresponding to the zero and maximum (N) number in the reversing counter 9 are connected to the sum | ruyush, it is subtracted to it, to the control inputs of the reversible counter 9. The multiplying device 7, the pulse generator 8, the reversing counter 9 and the decoder 10 together constitute a circuit for generating from the step voltages supplied to the inputs 11 and 12 ic of the outputs of the peak Choruses 5 and 6, linearly varying interiolation, its voltage (Uv, is the result of demodulation of AIM signals. The demodulator of AIM signals works as follows. In the initial state, trigger 2 is in zero position. In this case, the coincidence circuit 3 open, and the soviaden 4 circuit is closed. The first SR sync pulse arriving at the demodulator input passes through a coincidence circuit 3 at the peak detector 5, to another input of which at the same time the first input pulse of the PIM signal arrives. At the output of the peak detector 5, a voltage L / 1 is then set equal to the amplitude of the first pulse AIM (Fig. 2). The SI sync pulse, via delay element 1, also enters the counting input of flip-flop 2 and sets it to one state (the third diagram in Fig. 2), as a result of which the coincidence circuit 3 closes and the coincidence circuit 4 opens. The second SR clock pulse through the coincidence circuit 4 now arrives at the peak detector 6, at the output of which a voltage Uz is set, proportional to the amplitude of the second pulse of the AIM signal, which enters simultaneously with the second clock pulse. The second clock pulse through the delay element 1 also enters the trigger 2. And sets it to the zero state; coincidence circuit 3 opens and peak detector 5 is prepared for iriem of the third pulse AIM. When iIPSTbero receives an impulse of PIM, the output voltage f / i of the hygiene detector 5 changes and becomes equal to the amplitude of the third PIM pulse. Further work of this part of the demodulator is similar to that described. Thus, at the output of the peak detector 5, a stepwise voltage Ui is formed, resulting from the extension of the odd-numbered AIM Signal signal by two clock periods, and at the output of the peak detector 6 is the voltage U, which is the result of a similar expansion of the even-numbered pulses. The voltages L / i and U are fed to the analog inputs 11 and 12 of the digital-analog multiplying device 7 operating in the interpolator mode. In the initial state (before the first pulse AIM pulse arrives at the demodulator) in the reversible counter 9 there is a zero number and it is prepared for the summation mode. At the same time, at the output of the multiplying device 7 connected to the reversible counter, the voltage (/ output is equal to the voltage Uz, arriving at input 12. When the series of pulses from the generator 8 arrives, the number in the reversing counter 9 increases evenly. a linear change in the output voltage of the multiplying device 7 or the voltage level at the input 12 to the voltage level at the input 11. At the moment when in the reversible counter 9 the number reaches the maximum value N, the voltage of the voltage becomes equal to the voltage and the input 11. At the same time, the output L of the decoder 10 produces a pulse that switches the reversible counter 9 to the subtraction, as a result of which the number in it starts to decrease. Decrease the number in the reversing counter Causes the output voltage of the multiplying device to vary linearly This input is continued until the reverse counter has a zero number, and the voltage t / o reaches the voltage level at input 12. At this point, left decoder 10 output pulse is generated, which translates down counter 9 in summing mode. In the following, the circuit works cyclically. The frequency of the pulses of the generator 8 is chosen such that the time for filling the reversible counter 9 from zero to the number L or reducing from the number N to zero is equal to the clock period T of polling the channels (the period following the pulses of the PIM signal). When cyclically changing the number in a reverse counter from zero to N (odd clock periods) and from L to zero (even clock periods), the output voltage of the multiplying device will vary linearly from the voltage level at input 12 ((/ 2) to voltage level at input 11 (Ui) and back from level Ui to level 1/2. Figure 2 shows the voltage diagram of f / Bbix for the case when the reversible counter has three binary digits. In the same diagram on the x-axis The current number in the reversible counter is marked. If necessary, 1 : a. Step-down linear voltage iK is purely linear, this can be achieved by increasing the number of bits of the reversible counter.Thus, the demodulator shown in Fig. 1 provides demodulation of amplitude-modulated pulses using piecewise linear approximation. The use of this demodulator instead of the known demodulators that implement stepwise approximation, and can significantly reduce the amplitude distortion of the useful Signal.

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Claims (3)

1. A demodulator of amplitude-modulated pulses containing two parallel-connected controlled peak detectors, the information inputs of which receive a signal of amplitude-pulse modulation, characterized in that, in order to reduce the amplitude distortion of the useful signal, to the control inputs of the above-mentioned infrared detectors a circuit for separating the sync pulses into even and odd numbers is connected, with even sync pulses receiving the equalizing input of one detector and odd ones to the control input of the other; and at the output of the nick detectors, a circuit is established for generating an interpolating signal. 2. Demodulator by TI. 1, characterized in that the separation circuit consists of a series-connected delay element, the sync pulses of iodana, a trigger, the counting input of which is connected to the output of the delay element, and two And circuits, one input of each of which is connected to the corresponding trigger output, and to the other inputs of the iodine there are clock pulses, with the outputs of the AND circuits being connected to the control inputs of the respective peak detectors. 3. A demodulator according to claim 1, of tl and chas with the fact that the formation consists of, iOnly connected generator of impulses and a reversible counter, the output of which is the keys to the inputs of the multiplier the device and the decoder, the outputs of the latter are connected to the control inputs of the reversible counter.