SU441592A1 - Associative memory element on mop transistors - Google Patents

Description

the invention of O2nos sy to vapom "to those who teach devices,

The attributes of the associative code on the elements of the MOS-1 are crisis, 10 containing the trigger, the log-and-loop scheme, consisting of the Grandsors, whose hooks are connected to the corresponding 5th shoulder of the trigger, the gates - to the origin of the tires, and

key transistor control u.

transistors and number bus,

However, in such elements of the day the output of the output signal is read and compared, a change in voltage at the shoulder of the triB is required. Hera, that may. Lead to destruction information, besides, in. . known elements are used, additional power sources and busbar control devices

1 Purpose of Invention — Simplification

{associative memory storing mbntaI exclusion of the possibility of destruction of information when reading and comparing

This is achieved by the fact that, in the electronic unit, control transistor drivers are connected to the corresponding trigger arms, sources - to the bit buses, drains - to the number bus connected to the gate of the key transistor, the source of which is connected to the common SHIE element

The drawing shows a diagram of an associative memory element.

Zlbment contains active 1.2 load 3.4 MOS granzistors, forming a static trigger, granzistors 5, 7, realizing a logic circuit. Unequivocally CTb j transistor 8 and transistor 7 - key, pfadoiaei in the key mode Gates of the controlling transistor 8 and 9 are connected to the respective arms of the Yu-11 trigger, sources to the bit buses 12 and 13. Drains to the numerical band IA- connected to the gate of the transistor 7. The source of which is connected to the common bus i5 element. The element operates as follows. In storage mode, bit 12, 13, and number 14 buses are at a low potential, providing a closed part of the transistors 5-9, the trigger is in the set position and isolated from the tires I2, i3 and 14. The trigger condition changes during recording, if the information stored in it is opposite to the recordable one, which is achieved by connecting the trigger arm with a high logical voltage level to the common bus 15 via transistors 5 and 7 OR 6 AND 7. At the same time, the recorded information in paraphase form is supplied On the bit buses 12 and 13, opening the transistor 5 or 6 on the gate, realizing the function Unequivalence stored in the trigger and the input information. The element is sampled by applying a high logic level to wi & KS 14, which causes the gate of transistor 7 to be allowed to write, and to supply power to the drains of transistors 8 and 9 when read, Depending on the trigger state, transistor 8 or 9 is in the open state on the gate. When reading, the current flows from the word line 14 through the open transistor B or 9 to one of the bit lines 12, E3, which are at a low potential, fixing the state of the element at the output. In the comparison mode, the external information is supplied in vapor form to the bit buses 2 and 13 so that in case of a discrepancy stored in the trigger and external information from the corresponding bit bus 12 or 13 through the transistor 8 or 9, the current flows to the word line 14, schuschus under the potential of them. “Subject of the invention. An associative memory element on M011 transistors containing a trigger, a logic circuit. Non-equivalence consisting of transistors whose drains are connected to the corresponding trigger arms, gates to bit buses, and sources to the drain of a key transistor, control transistors, numerical bus, characterized by the fact that, in order to simplify the element and eliminate the Boxmoxity of the destruction of information when comparing and comparing, the gate, the control transistors are connected to the respective trigger arms, and toki- to the bit lines, flows - to the wordline,: manager that is connected to the gate of the transistor, the source of which is connected to the common bus elzmanfO |.