SU767839A1 - Multistable dynamic memory member - Google Patents

Description

The invention relates to computing technology. It can also be used in the construction of random access memory devices. , Multistable phase-pulse memory elements are known, which contain a memory capacitor, two diodes, a charge, discharge and readout node. . . Their disadvantages are the complexity of the design and the impossibility of arbitrary sampling. Other sanoNiMHaKflJiHe elements are known that contain a field effect transistor c. double shutter; one of the closures is insulated and serves to store the charge, and the other is control. Such a design allows storing charges of various quantities, which increases the information capacity of the storage element. . This storage element, however, has a long recording time and a hard burn design. The closest technical solution to the invention is a dynamic storage element containing an information transistor, the gate of which is connected to the first output of the storage capacitor and the source of the recording transistor, the drain of the information transistor is connected to the source of the reading transistor, the drain of which is connected to the drain of the recording transistor and connected to the bit bus, the gates of the write and read transistors are connected respectively to the write and read buses, and the second vs output is memorized the first capacitor and the source of the information transistor connected to zero potential bus. The disadvantage of the total storage element is small information capacity, since it allows storing only 1 bit. information. The aim of the invention is to increase the information capacity of the memory element by ensuring the storage of several bits of information,. This is achieved by introducing a reference potential mine into the proposed dynamic storage element, which is connected to the source of the information transistor. FIG. 1 shows the electrical circuit of the proposed multi-stable dynamic storage element;

in fig. 2 is a time diagram of the readout process (Up.a is the voltage on the discharge bus; Don the voltage on the reference voltage supply bus).

The multistable dynamic storage element contains an information transistor I, readout transistor 2, reference potential bus 3, write transistor 4, storage capacitor 5, discharge bus b, read bus 7 and write 8, bus 9 of zero potential.

the normal functioning of the breaking element is ensured by performing the modes of recording information, storing information, reading and regeneration.

In the recording mode, and the information on the bus 7 readings of information, a low level is applied, the bus 8 is written to a high level, and the discharge bus b is supplied to the voltage level to be recorded in the cell. The write transistor 4 is opened, and the capacitive terminal of the capacitor 5 is charged, to the level of the voltage corresponding to the recorded information and proportional to the threshold voltage of the transistors. Before the end of the write cycle, the write bus 8 is supplied with a low level, the write transistor 4 is closed and the storage element switches to the information storage mode, which is also characterized by the locked state of the read transistor 2.

In the information storage mode, the storage capacitor 5 is isolated from the discharge bus 6 and the information is stored in the form of a charge, the value of which is proportional to the recorded voltage. For an eight-stable memory element, one of the voltage levels is stored on the storage capacitor 5; For example, when storing the first voltage level, its value is equal to three times the threshold voltage of the transistors.

In the mode of reading the information of the discharge of the bottom, the bus b is precharged to a high level, the highest potential potential is supplied to the bus 3 of the reference potential, and a high voltage level is fed to the bus 7 of the readout. Then the reference potential decreases in a stepwise manner, and the information transistor 1 opens only at the moment when the stored voltage level of the supports is exceeded.

It has a potential of a magnitude greater than the threshold voltage of the transistors. This moment is detected by the read amplifier, and the information is recognized by the time interval in which transistors 1 and 2 are opened (see Fig. 2).

B in the mode of regeneration of information, which is carried out in two stages, first reads

0 stored information, and then re-write it.

Claims (1)

Invention Formula A multistable dynamic storage element containing an information transistor, the gate of which is connected to the first output of the storage capacitor and the source of the writing transistor, the flow of the information transistor is connected to the source of the read transistor, the drain of which is connected to the drain of the writing transistor and connected to the bit 5, the gates of the write and read transistors are respectively connected to the write and read buses, the second output of the storage capacitor is connected to the zero potential bus, characterized in that, in order to increase the information capacity of the element, a reference potential bus connected to the source of the information transistor is inserted into it. .