JPH03125398A - Semiconductor nonvolatile storage element - Google Patents

Abstract

PURPOSE:To increase the logical amplitude of the voltage of an output terminal and to decrease the number of elements by utilizing a bootstrap inverter. CONSTITUTION:The input part of the bootstrap inverter 6 is formed of a floating gate type N channel transistor(TR)N1 connected to a word line W and when the word line W is raised without injecting any charge in the gate of the N1, the TRN1 turns on to short-circuit the output terminal 4 to the ground, so that a logical value 0 is obtained at the terminal 4. On the other hand, when an enable signal E is raised and a high voltage is applied between a bit line B and the line W, charges are injected into the gate of the TRN1 and the threshold value increases. Therefore, even when the line W is raised, the TRN1 does not turn on and the terminal 4 is disconnected from the ground; and the potential at the terminal 4 is raised almost to a power source potential VDD by the inverter 6 to surely apply a necessary voltage to a logic gate. Further, gate. Further, the constitution which uses the bootstrap inverter increases the number of elements to increase the degree of integration.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor nonvolatile memory element that stores data in a PLD (programmable logic device), etc. It is designed to be thicker and use fewer elements.

[Conventional technology]

In PLO, etc., it is necessary to convert the data stored in the semiconductor nonvolatile memory element into an electrical logic level so that it can be directly supplied to the logic gate.The conventional circuit configuration is shown in Figure 2. There was something to show.

That is, the word line W is connected to the control gate of a floating gate type N-channel MOS transistor (hereinafter referred to as an NMOS transistor) N+, and the bit line B is connected to an NMOS transistor Nz whose gate is supplied with an enable signal E. It is connected to the high potential side of the NMOS transistor N through
The high potential side of the transistor N is connected to the output terminal 4 via a latch circuit 3 having inverters 1 and 2 crossed over each other.

Now, assuming that no charge is injected into the floating gate of the NMOS transistor NI (it is in a non-write state), the threshold voltage of the NMOS transistor N1 is a normal value (about 2V), so the word line cannot rise. For example, NMOS transistor N1 is turned on.

Therefore, the storage data Q of the latch circuit 3 has a logical value of "0".
Since the inverted data Q2 has a logical value of "1", the output terminal 4 is held at a high potential.

Furthermore, the enable signal E is raised to turn on the NMOS transistor N2, and appropriate voltages are applied to the bit line B and word line W to inject negative charge into the floating gate of the NMOS transistor N (to set it to a write state). , the threshold voltage of the NMOS transistor N rises, so even if the word line W is turned on after that, the NMOS transistor N
MOS transistor N maintains an off state.

Then, the potential of the stored data Q, of the latch circuit 3 rises to the logical value "1", and the inverted data Q, becomes the logical value "1".
0'', the output terminal 4 is held at a low potential.

Furthermore, in order to read data from the bit line B, the word line W is raised and the enable signal E is raised to conductively connect the bit line B to the high potential side of the NMOS transistor N. Since the NMOS transistor N'+ is off, the bit line B has a high potential, and in the non-writing state, the NMOS transistor N,
Since the bit line B is on, the potential of the bit line B becomes low, so the data stored in the memory element can be known based on the potential of the bit line B at that time.

Then, the charge injected into the floating gate is
This memory element is nonvolatile because it is stored regardless of whether power is supplied or not.

[Problem to be solved by the invention]

However, the conventional nonvolatile memory element described above has the following unresolved problems.

That is, each of the inverters 1 and 2 constituting the latch circuit 3 usually has two NMOS transistors as shown in FIG.
Consisting of transistors N, 3 and N4,
The gate of the NMOS transistor N on the power supply Vdd side is connected to the power supply Vdd, and the gate of the NMOS transistor N on the ground side is connected to the power supply Vdd.
4 is the input terminal 5, and the NMOS transistor N
, and N4 is used as the output terminal 6.

Therefore, if the input terminal 5 is at a high potential, the NMOS transistor N4 is turned on, so the output terminal 6 is connected to ground and becomes a low potential, and if the input terminal 5 is at a low potential, the NMOS transistor N4 is turned on.
Since OS transistor N4 is turned off, output terminal 6
is disconnected from ground and has a high potential.

In this way, it functions normally as an inverter, but since the NMOS transistor N as a load is interposed between the output terminal 6 and the power supply Vad, even if the NMOS transistor N4 is turned off, the voltage at the output terminal 6 is, NM
The voltage drop at the OS transistor N3 becomes lower than the power supply voltage.

Therefore, when the output terminal 4 of the latch circuit 3 is connected to a logic gate such as a PLD, sufficient logic amplitude cannot be obtained, so there is no room for absorbing noise and there is a risk that the logic gate may malfunction. Ta.

Furthermore, since the latch circuit 3 is configured using four transistors, it occupies a large area within the memory element, which significantly reduces the degree of integration of the PLD and the like.

The present invention has been made by focusing on the unresolved problems of the conventional technology, and has been made to develop a semiconductor in which the logic amplitude of the voltage at the output terminal is sufficiently large and the number of elements used is small. The purpose is to provide a nonvolatile memory element.

[Means to solve the problem]

In order to achieve the above object, in the semiconductor nonvolatile memory element of the present invention, the input part of the inverter of the hood strap is configured as a floating gate type MOS transistor layer, and the output terminal of the inverter of the hood strap is connected to a bit line. Furthermore, the control gate of the MOS transistor is connected to a word line.

[Effect]

When the floating gate type MOS transistor is turned off and the output terminal is disconnected from the ground, the output terminal becomes a high potential.However, in the present invention, since a food strap inverter is used, the potential of the output terminal is close to the power supply voltage. rises to.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. Note that the same parts and the like as those in FIG. 2 described in the related art are given the same reference numerals, and redundant explanation thereof will be omitted.

That is, in this embodiment, the inverter 6 of the hood strap
The output terminal 4 of is connected to the bit line B via the NMO3I transistor N2 whose gate is supplied with the enable signal E, and the control gate of the NMOS transistor N1 constituting the input section of the inverter 60 of the food strap is connected to the word line W. They are connected to form a semiconductor nonvolatile element.

The inverter 6 of the hood strap is connected to the power supply Vdd and N.
MO3I - transistor N, NMOS transistor N between
, and the power supply vtin is connected to the NMOS transistor N
6, its NMOS transistor N,
The gate of NMOS transistor N is connected to the power supply V a a, the gate of NMOS transistor N is connected to the source of NMOS transistor N&, and a capacitance C is connected between the source of NMOS transistor N6 and the drain of NMOS transistor N1.
This is a configuration with a

If the floating gate of the NMOS transistor N1 is currently in a non-write state where no charge is injected into it, when the word line W is turned on, the NMOS transistor N1 is turned on and the output terminal 4 and the ground are short-circuited. 4 is a low potential (logical value "0").

Furthermore, by raising the enable signal E and applying an appropriate high voltage to the bit line B and word line W, charge is injected into the floating gate of the NMOS transistor N, so that its threshold voltage increases. Therefore, even if the word line W is turned on, the NMOS transistor N is not turned on, so the output terminal 4 is disconnected from the ground.

At this time, the potential of the output terminal 4 increases due to the power supply Vaa, but in this embodiment, since the hood strap inverter 6 is used, the potential of the output terminal 4 increases by the power supply Vd.
It rises to the vicinity of d.

Therefore, when the output terminal 4 is connected to a logic gate such as a PLD, the voltage necessary for the operation of the logic gate can be reliably obtained, reducing the risk of malfunction and noise. If you do so, you will have more leeway.

Moreover, with the configuration of this embodiment, a normal EPROM (
Erasable Programmable Rea
d 0nly Memory) cell, two NMOS
Transistors N,,N.

Since it can be constructed by simply adding a capacitor C and a capacitor C, the number of elements required is smaller than the conventional memory element using the above-mentioned latch circuit, and the degree of integration is improved accordingly.

Furthermore, since the gate potential of the NMOS transistor N, which acts as a load, becomes higher, there is also the advantage that the current gain can be increased.

Further, the semiconductor nonvolatile memory element of this example is a normal E
Since data can be written and read in the same sequence as PROM, it can be used for conventional PLO, etc., without major design changes.

Although this embodiment has been described using an N-channel MOS transistor as an example, the circuit can also be configured using a P-channel MO3I transistor.

〔Effect of the invention〕

As explained above, according to the present invention, a semiconductor nonvolatile memory element is constructed using a food strap inverter, so the number of elements can be reduced, which improves the degree of integration. Since the output voltage can be raised up to a level close to the current level, when the output is used in a logic gate, the voltage necessary for the operation of the logic gate can be reliably obtained, reducing the risk of malfunction. Various effects such as increased margin in the event of noise or the like can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of a conventional semiconductor nonvolatile memory element,
FIG. 3 is a circuit diagram showing the configuration of the inverter. 4... Output terminal, 6-... Hood strap inverter, N,... Floating gate type N-channel MOS transistor, N2 to N6... N-channel MO
S transistor, B... bit line, W... word line, C... capacitor

Claims (1)

[Claims] (1) The input part of the hood strap inverter is configured with a floating gate type MOS transistor, the output terminal of the hood strap inverter is connected to a bit line, and the control gate of the MOS transistor is connected to a word line. A semiconductor nonvolatile memory element characterized by: