SU432662A1 - CONTROLLED PULSE GENERATOR - Google Patents

Description

The invention relates to pulse generators and can be used in automation devices and digital computing technology.

A controlled pulse generator is known, containing a frequency divider, the output of which is connected to one control trigger input, and the input is connected to a crystal oscillator, and a trigger counter, whose input is connected to the output of the crystal oscillator via the AND-NO element.

However, in a known generator, only the intervals between pulses within a series of pulses are regulated, which limits its functionality.

In order to expand the functionality, a digital functional code converter is introduced into the proposed generator, the outputs of which are connected through additionally introduced coincidence circuits to the trigger trigger inputs, its output is connected to the second control trigger input, the latter output is connected to the second inputs of the coincidence circuit and the AND -NOT.

The drawing is a block diagram of the proposed generator.

The controlled pulse generator contains a frequency divider /, the output of which is connected to one input of control trigger 2, and the input is connected to a crystal oscillator.

3, counter 4 on the trigger 5i, 62, 5h. . . 5 ", the input of which is connected through the element" AND-HE 6 with the output of the quartz oscillator, the coincidence circuit 7i, 72, 7z ... 7 "and the digital function converter 8 code with input terminals 9, 9p, 9- .. . five". The outputs of the digital functional converter 8 through the coincidence circuit 7, / 2, 7z. . . 7 are connected to trigger inputs 5, 5, 5 ... 5 "counter 4, the output and the last - with the second input of the control trigger. The control trigger output is connected to the second inputs of the matching circuits 7i, 72, 7h. .. 7 „and the element“ AND-NOT 5.

The gated pulse generator gg follows.

From the output of the crystal oscillator to the input of the frequency divider, emulsions arrive at the following frequency / i, and the pulses at the output of the divider have the following frequency / 2 / iK, where K is the frequency divided coefficient.

The first pulse from the output of the delntel frequency, the incoming and single input of the control trigger, sets the last one to the state “. The potential signal at the output of the control trigger opens the element “AND-HE 6”, and from the output of the crystal oscillator to the counting input of the first trigger of the counter, pulses are received with a frequency of / 1.

At the moment of counter overflow, the signal that bridges from the output of the last trigger 5 ". of this counter to the zero input of the control trigger, sets it to the state "O. The potential from the output of the control trigger closes the "AND-NO" element, and the flow of pulses from the output of the crystal oscillator to the counting input of the trigger trigger 5i of the counter ceases. At the moment when the control trigger transitions from state "1 to state" O, a voltage drop occurs at its output; The same voltage drop occurs at the outputs of those coincidence circuits, at the second inputs of which there are logical signals "1. The voltage drops at the outputs of the 7i-7 coincidence circuits set the triggers to state "1 in those bits in which state" 1 already exists.

Thus, after overflowing the count of the pulses into triggers 5i-5p, the code of the person that is at the output of the digital function converter 8 of the code is written.

The process is repeated periodically.

The control trigger output signal is a pulse whose duration is determined by the counter overflow time.

The counter overflow time depends on the period T of pulses arriving at its input, on the number n of the counter triggers and on the number periodically recorded in the counter after its overflow. If the counter consists of triggers and the number L2 is already written in it, then for its overflow, 2 - L pulses must be sent to its input, while the number of intervals between pulses per unit is less than, i.e. 2 - L 2-1.

The pulse duration t at the output of the controlled pmpulse generator is determined with the expression

T 7, (2 -L2-1),

where N-i is the number at the output of the digital func- onal code converter g. In order for the pulse duration at the output of the controlled pulse generator to be proportional to the code of the input number in accordance with any predetermined law (t G | X Xf (lVi), it is necessary for the digital functional code converter to realize the dependence

.V2 2 -ff / V | J -1.

The pulse duration t in this case is related to the input number L, the ratio

t G, .f (.

If, for example, it is necessary that the duration of the pulses at the output of the controlled generator be proportional to the square of the input number 5t G ,.

then the digital function code converter 8 must implement the form dependency

L2 2-L / -1.

Thus, at the output of the digital function converter, at any time there is a number expressed in the form of a binary-coded potential signal, proportional to the number at its input, also expressed in the form of a binary-coded potential signal, according to a given functional dependence.

The signal at the output of the element "AND-NE 6 is a series of pulses, the following with a frequency of / 2. The number of pulses in a series is determined by the expression

t.

If the digital functional transform. Code implements the dependence of the form

L2 2 "- / (L,),

then the number of pmpulses t in the series is related to the input number L by the ratio

(N,),

where F (N) is any predetermined law of change in the input number.

Subject invention

A controlled pulse generator containing a frequency divider, the output of which is connected to one control trigger input, and the input is connected to a crystal oscillator, and a trigger counter, the input of which is connected through an H-NE element with a crystal oscillator output, characterized in that In order to extend the functionality, a digital functional code converter is introduced into it, the outputs of which are connected through additionally entered schemes of coincidence with the trigger inputs of the counter, the output of which is connected with the second input three ger control, the output of the last is connected to the second inputs of the coincidence circuits and the "I-NOT circuit.

Bi,