SU374597A1 - Sun-SS EHiib / - - Google Patents

Description

one

This invention relates to digital communication systems.

It is known a phasing device of a parallel-sequential | Vna-transducer, which contains a fa- tioning circuit and a gating circuit connected to the input terminal. The gating circuit, to which inputs are connected in series; the connected delay triggers, rear edge differential formers, a cumulative register and a shift register, as well as a source of impulses of the wired path, to one of the outputs of which are sequentially connected to the allocation circuit of the radio / nal interval and the phase discriminator, connected by one of the inputs to the outputs of the differential formers of the rear edges.

However, the known device has a low delay setting accuracy and Hie remembers delay values when the signal is interrupted, which is especially important under the conditions of the KB pa D | Yok, anala, when after the signal is frozen, the phase position of the radio channel pulses must be applied. in the same place as before | fade away.

The proposed device is different in that it contains a diamide trigger and a sequential control trigger, a counter, a scheme for setting initial conditions and a reversible counter, the inputs of which are added and subtracted from the phase discriminator, one of the elements of the scheme for setting initial conditions connected to the phasiO1v circuit: NIII No. is connected to a single control trigger input, the gating circuit input, and the start output of the d.nmichesky trigger, whose stop input is connected to the trigger trigger input laziness and an output connected to the input clock impulso.v counter output Attached to zero inputs of flip-flops and the flip-flop unra.vleni zaderl ki.

This allows to improve the noise immunity.

The drawing shows a block diagram of the device.

The proposed device contains input terminals / parallel subchannels of the radio path connected in parallel to the inputs of the phasing circuits, x subchannels 2 and gating 3. The parallel outputs of the gating circuit 3 are connected to single inputs of delay triggers 4, the outputs of which are connected to the differential shapers of the rear fringe 5 to the information inputs on the register register. 6,. Connected to the informational inputs of the shift register 7. Informational inputs of the register 6 are connected: to one input of the phase discriminator S, the second input of the discriminator 8 is connected to each of the radio channel clock interval from the reference impulses of the wired channel , one input of circuit 9;: connected to the source 10 of the reference impulses of the wired channel, and its second input is connected to the output of the circuit of the phyro | Ba.ni 2.

You 0 | D; Ы “4- and“ - the phase di-SCRIMIVATO. P 8 connects from the input and add to and turns of the reversing counter 1J, whose triggers are connected to the trigger inputs of the counter 13 with a reset circuit. The input of clock pulses of the counter 13 is connected to the output of the dynamic trigger 14, the input of which is connected to the output of the phasing circuit 2, which is also connected to the input of the gating circuit 5, unit control trigger 15 and the start condition of the initial conditions 12 of the ECU.

The output of the counter 13, connected to the reset input of the same counter, is also connected to the zero input of the control trigger 15 and the zero inputs of the delay trigger 4. The output of the control trigger 15 is connected to the residual input of the dynamic trigger 14.

The device works as follows.

At the terminals / u1st; roystv-no.cTynaieT there are several parallel streams of synchronous information. The phasing circuit 2 calculates the average value of the fronts of these streams and the output onoipHoe voltage on the gating circuit 5, enhances the input signal, and the gating result is fed to the trigger trigger 4 in the form of narrow pulses. The trigger 4 is reset from the counter 13, and the pulse duration of the triggers 4 determines the amount of delay that needs to be inserted into the input parallel signal in order to ensure the adjustment of this signal to the reference impulses of the wired channel. In differentiation schemes 5, the leading edges are selected. And these emulsions are written to cumulative register 6. Reading from register 6 is carried out by the reference impulse of the wired channel in the tact of the radio channel from circuit 9.

The parallel streams of a discrete signal at the moments of operation of the pulsed wired channel pulses in the form of a parallel code are transferred to shift register 7, with output, od | and which, the roto information is written off already in the following code, i.e., if parallel flows have a 200 baud rate of manipulation and are transmitted over 6 subcamps, then from the output of register 7, a 1200 baud signal is written off at the clock points specified by the source 10 of the reference pulses of a wired cable. Changes in the propagation time of the parallel subchannels

is produced discretely with the pulse frequency determined by the pulse frequency of the dynamic trigger 14, which is triggered by each | M reference impulse from the phasing circuit 2. Each |) GM reference pulse through the initial condition setting circuit 12 the reference pulse in the form of a parallel code is written into counter 13. View This parallel shoe is determined by the state of the flip-flop counter triggers, in which Za writes a code characterizing the magnitude of the phase one. disagreement I “between the impulses of the conductive. and radio channels. Depending on the number of initially written to the pulse counter 13, the time of the Zaatolian counter will change 1, and the output pulse of the counter 13, which sets the time interval of the dynamic trigger 14, will determine the value

delays introduced into the pa; parallel; real pods of the triggers 4. A pulse from the output of the counter 13 arrives simultaneously at the zero inputs of the delay 4 triggers and the zero input of the Zirav en1 trigger. 15 implementing

stopping the dynamic trigger 14.

Subject invention

A device for phasing parallel-to-serial | tel transform, containing 1 phasing and gating circuit, connected to the input terminals of the circuit 1, to the gating circuit. which connects serially connected flip-flop triggers, back-front differential generators, a cumulative register and shift register, and also: the source of wire path pulses, to one of the outputs of which is a taiga interval selection circuit and a phase discriminator connected by one of the inputs to the outputs rear differential gear shapers, characterized in that, for the purpose of elevating Nomeh durability, it contains a dynamic trigger and three consecutively control germ., counter1K, initial conditions assignment scheme and CHBiHbm counter, whose addition inputs and subtracts are connected from the outputs of the phase discriminator, one of the inputs of the assignment diagram n: the initial conditions of the nodes | key to the output of the phasing scheme and connected to the output. control trigger, input.m

a gating circuit and a trigger input for a dynamic trigger whose stop input is connected to the control output Oj TjpHirrepai, and the output is connected to the input clock of the counter, connected to the output

to the zero inputs of control trigger 1 and delay triggers.

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