SU373733A1 - YSESOYUPN '- ^ -' V g • '• - ^' ^ 1 '• •• • - Google Patents

Description

one

Devices for extrapolating functions defined by a digital code, containing first and second memory cells connected in series, whose inputs include a delay line, and large-scale resistors are known.

A disadvantage of the known devices is low extrapolation accuracy.

The proposed device is characterized in that it comprises a third memory cell, the inputs of which directly and through an additional delay line are connected to the inputs of the second memory cell, and a digital-analogue computing unit of polynomials, one of the inputs of which is connected to the input terminal, two other inputs are connected through the scale resistors to the inputs of the memory cells, and the output is connected to the output terminal of the device and through the scale resistor is connected to the output of the first memory cell.

This makes it possible to significantly increase the precision of extrapolation.

The drawing shows the block diagram of the device.

The device contains memory cells 1, 2 and 3, a digital-analog block 4 for calculating polynomials of the form. - -In - {- C, additional 5 and main 6 delay line, scale resistors 7-11. Numbers 12–15 respectively denote the inputs: the ordinate code of the extrapolated function, the code of the prefixed argument value, the pulse of the end of the next extrapolation interval, and the output of the extrapolated function. Numbers 16 and 17 are designated

coefficient inputs / 1 and S of block 4.

The memory cell / is designed to receive the ordinate code of the extrapolated function, input to the device 12, generate direct and inverse (antiphase) voltages proportional to this code, and transfer the code of the previous ordinate of the extrapolated function to the memory cell 2. The direct output of the memory cell / is associated with the inverse output of the memory cell 2 and through the scale

resistors 7 and 8 - with inputs 16 and 17 of the coefficients A and B of the digital-analog block 4 for calculating polynomials. The second direct output of the memory cell / is connected via a large-scale resistor 11 with an output of 15, and an inverse output

connected to the direct output of the memory cell 3 and through the scale resistors 9 and 10 to the inputs 16 and 17 of the block 4. The digital output of the memory cell / is connected to the input of the memory cell 2, and the input of the reset state to the output delay lines 6.

The memory cell 2 is intended for receiving a code arriving at its input from the output of the cell /, and generating an inverse voltage proportional to this code. The digital output of this cell is connected to the input of the third memory cell 3, and the zero-state input is connected to the input of delay line 6 and the output of additional delay line 5.

The third memory cell 3 is intended for receiving a code arriving at its input from the output of memory cell 2 and generating a voltage proportional to this code. The installation input to the zero state of this cell is connected to the input 14 of the device and the input of the additional delay line 5.

Digital-analog block 4 is designed to receive the code of the anticipated value of the argument input to input 13, and to calculate POLYNOMES of the form g / LL: 2- | -In + C taking into account the coefficients A, B and C, arriving as voltages at its inputs 16 and 17 and output 15. Output 15 of block 4 is the output of the device, at which an extrapolated function is obtained in the form of analog voltage.

The additional delay line 5 is intended for delaying the pulse of the end of the next extrapolation interval by the time determined by transients in memory cell 3 occurring at the moments of the latter being set to the zero state.

The delay line 6 is designed to delay the pulse arriving at its input from the output of the additional delay line 5 for the time determined by the transients in memory cell 3, which arise when the cell is set to the zero state.

Subject invention

A device for extrapolating functions defined by a digital code, containing in series first and second memory cells, between the inputs of which a delay line is included, and scale resistors, characterized in that, in order to improve accuracy, it contains a third memory cell, the inputs of which directly and through an additional delay line are connected to the inputs of the second memory cell, and a digital-analogue polynomial calculation unit, one of the inputs of which is connected to the input terminal, the other two inputs are connected through the mas -scale resistors to the inputs of the memory cells, and an output coupled to the output terminal

device and through a large-scale resistor connected to the output of the first memory cell.