SU368604A1 - DEVICE FOR PROGRAM INTERRUPTION - Google Patents

Description

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This invention relates to the field of computing.

Devices for interrupting programs are known, including an interrupt register, a protection register, an enabled interrupt detection circuit, a counter, a decoder, and a control circuit.

The disadvantages of the known device are the lack of control over the operation of the device and the low reliability of the information received from the device.

The aim of the invention is to ensure complete control of the operation of the device.

The goal is achieved by including a modulo adder, gates, convolution schemes, a security check code register, an OR circuit, a logic circuit, an interrupt number register, and an interrupt number control code register.

The scheme of the proposed device is shown in the drawing.

The device contains a control circuit 1, an adder 2, designed to add modulo a number of residual codes, interrupt register 3, the first group of gates 4, the first convolution circuit 5, protection register 6, security check code register 7, detection of allowed interrupts 8 , a group of circuits "OR 9, a second group of gates 10 for interrogating all of the interrupt bits. and detecting the higher priority of the allowed

interrupt, counter 11, decoder 12, third valve group 13 for interrogating the OR circuit group, the second convolution scheme .14 for calculating the residual code from the allowed interrupt code, logic 15 for generating an allowed interrupt detection signal and residual code from the detected number raz da

interrupt number, interrupt number register 16, interrupt number check code register 17, third convolution scheme 18 for calculating the residual code from the logical sum of the interrupt code and the protection code, the fourth group of gates 19.

The interrupt signals input to the device input 20 are recorded. At the corresponding bits of the interrupt register 3, as well as

pass through the first group of valves 4 to the first inputs of convolution scheme 5. Convolution scheme 5 generates a residual code modulo the control from the interrupt code, which is formed from F interrupt register 3, by adding ps

the module of the bit interrupt signals taking into account the weight value of the corresponding bit. The first group of valves 4 through the second input is controlled by a signal from the output of the interrupt register 3 in such a way that the valves corresponding to the 3 interrupts recorded in the left interrupt register are closed.

Security register 6 and the security check code register 7 are written to the security device input to the device // and its control code, which is the code of the remainder of the 1PO module. The outputs of the inverse codes of the interrupt register 3 and the protection register 6 are fed to the inputs of the detection circuit for enabled interrupts 8, and the outputs of the forward codes of these registers are fed to the input of the OR 9 circuit group, which form the logical sum of the interrupt and protection codes . The code of allowed interrupts from the output of the circuit 8 is fed to the first input of the second group of valves 10, and the code of the logical sum from the output (The group of OR 9 circuits to the first input of the third group of gates .13.

The detection of the higher priority allowed interrupt is carried out by sequentially issuing polling signals to the second input of the second, group of valves 10, starting with the valve corresponding to the preceding priority of the discharge. The polling signals are generated by the counter 11 and the decoder 12 as a result of issuing a series of pulses from the output of the control circuit to the counter input. The polling signals from the output of the decoder 12 are passed to the second inputs of the second group of valves 10 and the third group of valves 13.

Simultaneously with the issuance of pulses to the input of counter 11 from the output of the control circuit, pulses are fed to the input of adder 2 to form a residual code from the counter code necessary to perform the monitoring.

Until the detection of an enabled interrupt from the output of control circuit 1, a prohibition signal is received at the input of the second convolution circuit 14 and at the input of logic circuit 15. If an interrupt is detected from the output of one valve from the group of valves 10, a signal is output to the first input of logic circuit 15 and the second input of convolution circuit 14. In this case, the circuit 15 forms a signal at the first output, which is transmitted to the input of the control circuit 1. On this signal, the control circuit / stops outputting pulses to the input of the counter 11 and the adder 2, generates a signal at the output that rewrites the contents of the counter 11 into the number register interrupt 16, and the contents of adder 2 from the output to the control code register number of interrupt number 17 (which is necessary to memorize the number of the detected interrupt bit and its control code at the time of monitoring), removes the prohibition signal from the inputs of the convolution circuit 14 and from the circuit 15. As a result of the removal of the prohibition signal from the input of the circuit 15, at its first output there appears an inversion of the modulus of the remainder from the number of the detected interrupt bit that passes to the input of the adder 2

It is the code of the remainder of the counter code. As a result of the removal of the prohibition signal from the input of the second convolution scheme 14, the code of the remainder of the number corresponding to the detected interrupt bit is recorded in it. After completing the sequence of actions listed above, the control circuit / continues to emit pulses to the INPUT of the counter / V to poll the remaining gates of the second 10 and third

1.3 valve groups. Thus, by the end of the survey, in the second convolution scheme 14, a modulo remainder code is generated from the allowed interrupt code, which is the logical product of the protection code and the terminator code, and in the third convolution scheme 18, the residual code of the number, which is the logical sum of the protection code and interrupts.

At the end of the survey on the signals coming from the output of the control circuit /

the input of the adder 2, is carried out sequentially adding modulo the information transmitted from the output of the second convolution scheme 14 to the input of the adder 2 in the reverse code, the information transmitted from the output of the first

convolution circuit 5 to the input of the adder 2 in the forward code, information transmitted from the output of the third convolution circuit 18 to the input of the adder 2 in the reverse code, and information transmitted from the output of the register 7 security control code to the input of the adder 2 in the forward code. The result of adding the codes from the output of the adder 2 is fed to the input of the control circuit /. If the code received from adder 2 is equal to the control module, then control circuit 1 overwrites the contents of register .16 number of interrupt number into counter 11 and outputs a signal to the input of the fourth group of gates 19, at which at the output of one of the gates corresponding to the interrupt whose number is stored in the counter 11, a pulse is generated. This pulse resets the corresponding bit of interrupt register 3 and subtracts the contents of the first convolution scheme. 5 codes

the remainder corresponding to the discarded bit. At this point, the device finishes its operation, and the interrupt number code and its control code can be read from the outputs 22 and 23.

If a fault or failure occurs in any of the device circuits, the code formed in adder 2 is not equal to the module. In this case, the signal from the output of the control circuit 1 resets the counter 11, the adder 2 of the third convolution circuit 18 and prohibits the input of the logic circuit 15 and the second convolution circuit 14. Then the entire cycle of operation of the device is repeated. If, after the repeated cycle, the code in the adder 2 is not equal to the module, then the control circuit 1 outputs the error signal.

Subject invention

A device for interrupting programs that contains the interrupt register, the protection register