SU341029A1 - - Google Patents

Description

The invention relates to the field of computer science and computational technology, and is intended to form a sequence of pulses, the time intervals between which vary in accordance with the binary code of the number of input pulses.

A coder is known that contains an input pulse counter, a census scheme, an interval counter, a control trigger, an initial interval counter, an AND circuit, a clock pulse generator, and a circuit for forcing an initial interval counter to its initial state (after the overflow pulse of the interval counter) generating a setting pulse of a certain duration depending on the frequency of the synchronizing pulses.

The proposed device differs from the known ones in that it contains an additional AND circuit, connected via inputs to the second control trigger output and clock generator output, and on the output to the input of the initial interval counter.

This allows the device to be simplified by eliminating the scheme of forcing the initial interval counter to its initial state.

The device contains a clock generator}, an AND 2 circuit, an interval counter 3, a census circuit 4, an input pulse counter -5, an additional AND 6 circuit, a control trigger 7, an initial interval counter 8, an input pulse bus 9.

The device works as follows. The pulses from 1 generator 1 are fed to the inputs of the circuits "And 2 and 6. However, it can open

be only one of them. Let at the moment the signal from the first output of the trigger 7 (Fig. 2.6) open the “And 2” circuit, then the synchronizing pulses arrive at the input of the counter 3. By the same time moment in

counter 3 is recorded some number m, then after (2 - m) clock cycles of pulses (where n is the number of triggers of counter 3) at its output, the overflow pulse (Fig. 2, (3) is output. This pulse will change the state of the trigger 7. The circuit “AND 2 will close, and the circuit“ AND 6 will open. Then the pulses from the output of the generator of synchronizing pulses 1 arrive at the input of the counter of the initial interval 8. After the previous

the operation cycle of all the triggers of the counter of the initial interval 8 is in the zero state, therefore the overflow pulse at its output appears through Go 2 clocks of synchronizing pulses, where k is the number of torque and, therefore, the & 6 circuit closes and the And 2 will open.

At this point, the counter of the initial interval 8 is in the zero state, and the counter of variable intervals 5 records the new number t + / ("if, in the case of 0 | sibling account, t - /), where / is the number of input signals received to the input of the counter 5 on the bus 9, for a time equal to one last cycle of operation. Consequently, the pulse of the overflow of the counter 3 in Vits through 2 - (t H- /) clock pulses. The census impulse to scheme 4 comes from the counter of the initial interval 5 somewhat earlier than the pulses of its overflow appear. The process then repeats, i.e. the interval between pulses at the output of counter 5 (see Fig. 2, e) is described by the formula

G, Go + SNi,

where TI is the interval between the output pulses of the device;

Go - the initial time interval;

 - the number of input pulses received by the device at the time of the signal of the 1st time interval;

5 — the slope of the change — the intervals, depended on w, and on the ratio of the frequencies of the synchronizing and input pulses.

FIG. 2 - output signal diagram

clock generator

marked by the letter a, the scheme "And 2 - in the scheme

"And 6 - g, the counter of the initial interval - e.

Subject invention

An encoder containing an input pulse counter, the outputs of which through a census scheme are connected to the inputs of an interval counter, the output of which is connected to the input of a control trigger, to another input of which

the output of the initial interval counter is connected, the other output of which is connected to the input of the census scheme, the clock generator connected to the input of the AND circuit, to another input — the first output of the control trigger is connected, and the output of the AND circuit is connected to the interval counter input that differs that, in order to simplify the device, it contains an additional AND circuit connected at the inputs to the second

the output of the control trigger and the output of the generator of synchronizing pulses, and the output of the output - with the input of the counter of the initial interval.