SU318948A1 - DEVICE FOR DISTRIBUTING MEMORY OF MEMORIZING DEVICES - Google Patents

Description

The invention relates to the field of computing.

Devices for allocating memory based on list structures are known, combining free zones using a valuable list. In this case, the issue of numbers for recording (excluding a member from the list) is performed from the beginning of the list, and the inclusion of the vacant storage area (storage) is performed at the end of the list. Such a distribution device is quite simple, has a high speed and is widely used in computer systems.

The disadvantages of the known devices are, firstly, the too large amount of memory required to store the list,

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where I - the number of zones in the memory center; secondly, low reliability. Indeed, one failure is enough at any of the communication addresses, and the list is completely or partially destroyed, which means the loss of all or part of the zones for the center. Since, in message switching centers, as in any real-time systems, reliability requirements are particularly high, this disadvantage of the list distribution device becomes very significant, and the possibility of accumulating

errors in such a device during continuous operation of the center practically exclude the expediency of its use without multiple redundancy.

The purpose of the invention is to increase the reliability of the distribution device while reducing the amount of its memory.

The goal is achieved by assigning one memory element to each zone of the switching center memory, with one state of the element corresponding to the occupation of the zone assigned to it and the other state of the element to the non-occupancy of the zone. Thus, the number of elements necessary for the implementation of the device

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The bit depth of the memory cell. Each element has its own code address, defined as a cell address code and a code for the sequence number of an element in a cell. The code address of the element obtained in this way is equal to the code number of the center's memory zone. The search for a free zone is carried out by

sequential enumeration of cells and bits in the cell. The code address of the element of the empty zone is entered into the register, and for the purpose of speeding up the search is continuous, and the found code addresses of the gystras intended for storing the free zone codes, i.e., a certain amount of free zones is created. In order to enable the table to be searched and corrected offline, the table is stored in a separate storage device from L cells. Such an arrangement of the table allows you to select a storage device with sufficiently high speed and high reliability, since almost 1024, / 8-16 , L 128-64. In the case of smaller R, the table can be implemented on trigger elements. The drawing shows a block diagram of the proposed memory distribution device. Before starting work, all elements of the storage device 1 are set to the state "1, which corresponds to the empty of all memory zones; the zone counter 2, the exchange register 3, the free zone registers 4, 5, the register of the freed zones 6 are reset to the initial state corresponding to the empty word storage. The zone 2 counter is intended to form the cell address in the memory and the bit number in the cell and is a conventional trigger meter consisting of two parts: the low i counter with a capacity of i 30 and the high bit counter with a capacity of N. Low and high counters the bits have split counting inputs 7 and 5. The contents of the lower bits can be transferred to the decoder 9, and the contents of the older bits - to the register 10 of the memory address. Any memory device (2D 3, 2-D on various elements) providing the required technical parameters can be used as a storage device. The contents of the memory cells 1 are rewritten via the number register into the exchange register 3, which is designed to receive a word, store it for the time it analyzes its changes, and 45 then transmit it to the number register. The exchange register contains / triggers, the register of released zones 6 - P triggers (P - QgzR) is divided into two parts: the lower bits on the K triggers (D logs /) and the oldest 50 bits on the M triggers (M logsA). Content older bits can be transferred to register 10 of the address of the memory; the contents of the lower bits can be transferred to decoder 9. Decoder 9 is a group of 55 schemes coinciding with K. inputs, has 1 outputs and is designed to convert the code from the 2 zone counter or register 6 free zones, a positional signal on one of the tires, than the actual The t-60 selects one of the / bits of the exchange register 2, analyzes and corrects it. 15 25 40 before the processor takes it and issuing it. The number of free zone registers is selected based on the ratio of the frequency of zone requests by the processor and the speed of the distribution device so as to reduce waiting time up to a given time. The free zone registers are the usual registers on P triggers each; parallel operation of these registers is controlled by the distributor 12, which ensures that the free zone code is recorded from the counter ka free zones in only one free register, if the registers are free, and issuing a code to the processor from only one busy register, if the registers are filled. The control unit 13 is a group of triggers and logic circuits and is designed to generate control signals for the device to operate in the free zone search mode and in the free zone reception mode. Matching circuit 14 is designed to analyze individual bits of the register of the exchange. In the search mode, the device operates as follows. To the group of most significant bits of the zone 2 counter, "+ 1" is added, and their contents are written to the memory address register 10. At this address in memory 1, the word is read, and the word from register 11 of the number of memory / is transferred to register 3 of the exchange. The reverse code of the word from the trigger register 3 exchange is sent to the dropdown circuit 15, and if the read word was empty (i.e., in all / bits of the word was written "O, which corresponds to the occupation of the corresponding zones), then in the group of high-order bits 2 zones are added "+ 1" and the word is read from memory 1 at the newly formed address. If the read word was not empty, then "+ b" is added to the group of lower bits of the zone counter. The resulting code is fed to the decoder 9, and the matching circuit 14 analyzes the contents of the 1st bit of the word. If "O (which corresponds to the zone occupancy) is written in the 1st bit, then" + 1 "is added to the group of lower bits, and the next bit is analyzed. If the analyzed bit contains" 1 (which corresponds to the unoccupied ), in this bit, the trigger is transferred to the "O" state, the contents of the zone 2 counter are sent to register 4 or 5, the "- | - 1" is added to the lower-order group of the zone 2 counter, and the next bit is analyzed in the same way Yes. Upon completion of the analysis of all / bits or by filling the registers 4 and 5 with free zone codes, the modified word is sent from the exchange register 3 to the 11th register of the memory number / address in the upper bits of the 2 zone counter, the -f-1 is added to the senior group In the disabled mode, until the registers 4, 5 of the free zones are filled, after which the modified word is sent to the register 11 of the number of the memory 1, and when referring to the next cell of the memory 1, its contents are analyzed. The found free zone is not fixed, but the word does not change and is sent back to memory 1.

If the "Receive," signal comes from the processor, if there is a code in registers 4, 5 free zones, the code is issued to the processor from one register, this register is reset, and the code of the free zone found later is written into this register. If by the time of the arrival of the signal "Issue none of the registers 4, 5 free zones there is no code, then the search for a free zone is carried out, as indicated above.

If in the process of searching for a free zone from the processor, the "Receive" signal is received, the analysis of the next discharge ends, operations are performed to change the word (if necessary) and send it to the memory 1, as described above, after which the distribution unit switches to reception of the vacated zone.

In receive mode, the device operates as follows.

The signal of the Register Receive 6 Register of Liberated Zones records the code of the vacant zone from the processor. The contents of the high bits of register 6 of the released zones are sent to register 10 of the address of memory 1, the corresponding cell is read, and its contents are transferred to exchange register 3. The contents of the low bits of the register 6 of the free zones are transmitted to the decoder 9, the corresponding output of the descrambler is excited and in the corresponding bit of the word placed in the exchange register 3, instead of "O is written" 1. The modified word is sent back to the memory / by the address of the high bits of the register 6 of the released zones, then the register 6 is reset to the initial value of the counter, is added "- | -1", and the device switches to the free zone search mode.

As follows from the description, the proposed memory allocation device requires for its realization a minimum memory size, since only one storage element is assigned to each zone. This allows elements of increased reliability to be used in memory. In addition, the principle of device construction ensures high reliability of the distribution of the center's memory: a failure in one category entails the loss of only one zone, and Hfe of a whole group of zones.

The required speed is provided both by the structure of the device (increase

the number of registers storing codes of free zones) and due to the continuous search for a free zone in the autonomous mode.

Subject invention

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A device for allocating a memory of memory devices, comprising a memory device, zone registers, exchange register, decoder, zone counter, logical

circuits and a distributor connected to logic circuits, characterized in that, in order to reduce the memory size and increase the reliability of the device, in it the outputs of the high-order bits of the register

zones and zone counter through the first circuit "OR connected to the inputs of the register of the address of the storage device, the outputs of the lower bits of the register of vacant zones and the zone counter through the second circuit" OR

connected to the inputs of the decoder, the outputs of which through valves are connected to the control inputs of the exchange register, the information inputs and outputs of the exchange register are connected respectively to the outputs and inputs of the memory number register and to the inputs of the first and second matching circuits, the output of the first matching circuit is connected to the counting input the higher bits of the zone counter, and the output of the second coincidence circuit - to the counting input of the lower bits of the zone counter; the outputs of the zone counter are connected via gates to the inputs of the registers of freedom dnyh zones.

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