SU1488800A1 - Device for dispatching tasks to processors - Google Patents

Description

The invention relates to computing and can be used in multi-machine and multiprocessor computer systems for load distribution between processors. The purpose of the invention the expansion of the scope of the device. The invention relates to computing and can be used in multi-machine and multiprocessor computer systems for load distribution between processors.

The purpose of the invention is to expand the field of application of the device due to the choice of processor, taking into account the volume of operations it performs.

Figure 1 shows the structural diagram of the proposed device; figure 2 - block diagram of the switch.

The device contains blocks 1 and 2 of memory, registers 3 and 4, counter 5,

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by selecting the processor based on the amount of operations it performs. A device for distributing tasks by a processor contains two blocks of memory, two registers, two counters, a multiplexer, a decoder, a register block, a switch, a block of AND elements, three OR elements, an AND element, two delay elements, a pulse shaper and a clock generator. During the operation of the proposed device, an analysis of the employment of processors takes place and the optimization of their load on the performance of the required functions. With a change in the number of processors and a change in the codes of functions, the circuit implementation of the block of logical conditions changes, optimizing the service process, 2 or less.

2 tab.

y—

decoder.6, element 7, 8 clock pulse generator, counter 9, multiplexer 10, driver 11 pulses, delay elements 12 and 13, elements OR 14 and 15, outputs 16-18, inputs 19-22, switch 23, block 24 AND elements, OR element 25, register block 26, OR element 27.

The switch 23 (FIG. 2) contains decoders 28-31, elements HE 32 and 33, elements AND 34-39, decoder 40, nodes 41-43 of elements AND, node 44 of elements OR, inputs 45-47 of the unit.

The device works as follows.

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Memory block 1 is designed to store the request queue, and memory block 2 is used to display the functionality of the processors. In this case, the cell of memory block 2 contains "I", if the s ~ processor is able to perform the function £ ', otherwise it contains "0"

(ί = 1,2,3, ..., Ν; a = 1,2,3 ..., M). _ten

Register 4 stores information about the busy processors: the 3rd discharge of register 4 contains "1" if the ^ -th processor is not busy, otherwise it contains "0". The reset of the 3rd discharge 15 of register 4 is performed by the device when loading ^ - processor, and writing to this bit "1" is done by the m processor when the service of the 20 request loaded into it is completed.

Before the distribution starts, the potential 22 is applied to the device input 22.

register 3, and resetting the block 26 registers through the element OR 27..

At the same time, before starting work on the distribution of requests for input 20, the request by the subscriber (the source of the request for 30 sows) is not issued and there is no signal to support the request (the inputs 20 of memory 1 contain a zero code). The inverse output of the first digit of register 3 contains "1" in this case, the transfer signal from counter 9, passing through the elements AND 7 and OR 15, is fed to the recording input of memory block 1. This signal records the "zero" code from inputs 20 to memory block 1 at the address from the output of counter 5 (the cell of memory 1 is reset at the address of counter 5). With some delay on element 12 on signal

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the transfer from the Y counter is increased by one unit of the contents of the counter 5. At the same time, the next transfer signal resets the next cell of the memory block 1, etc. After completion of the cycle- ^ 0 la (one or several) zeroing of all the cells of memory block 1, the subscriber can submit requests to the device for their distribution among the processors, $$ and by this time the signal from input ^ 22 is removed. The request and the tracking signal (the code of the requested function) is issued by the subscriber to the input 20.

When the first request is received, the inverse output of the first digit of register 3 is “1” (since the zero code is in register 3, i.e, the request intended for distribution was not issued from memory block 1), the sampling of multiplexer 10 does not occur and the transfer signal from counter 9 is transmitted through the AND 7 and OR 15 elements to the recording input of memory 1 (if there is a signal at the output of the OR 15 element, the code from the 20 input to the memory block 1 is written to the address from the output of the counter 5, and of this signal - reading from memory block 1 for the same address ECU). Thus, according to the transfer signal of counter 9, the request code from input 20 is written to memory block 1 at the address from counter 5 (the tracking signal from input 20 is written to the first bit of the memory cell, the contents of which are added to the first digit of register 3 when read). In addition, according to the transfer signal from counter 9 with a delay (the delay is determined by the recording time in memory block 1) on item 12, the contents of counter 5 are incremented by "1", and by this time the pulse signal at the output of the OR 15 element is missing and reading from the block occurs 1 memory. The signal from the delay element 13 '(the delay is determined by the reading time of the contents of memory block 1 at the new address from counter 5) resets the counter 9 and reads the contents of the memory block'] at the new address of counter 5 into register 3. The subscriber, having received the signal generated in the time of entering the request into memory block 1 (in the queue), removes (after recording in the memory) from the inputs 20 the request and, if necessary, sets a new one.

If the code from the cell of memory 1 containing the request ("1" in the first digit of register 3) is entered into register 3, then the inverse output of the first digit of register 3 displays "0", blocking element AND 7. and sampling multiplexer 10. When the arrival of each pulse from the generator 8 through the multiplexer 10 is a serial connection to the input of the sample block 2 memory bits of the register 4

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(information about the employment of processors from the first to the M-th).

As a result of the serial connection of the bits of the register 4 and when the sample is made in memory block 2, signals appear at its output. Upon receipt at the first input of the block 26 of the memory registers of the signal, the address of the free processor is written. The output signal from memory block 2 is generated if the processor defined by counter 9 is not busy (the signal from the output of multiplexer 10 samples the memory block 2) and is able to perform the requested function (the output of memory block 2 is "1" from its cell, the row address which comes from register 3, and the address of the column - from the output of the counter 9).

When conducting a cycle of the busy processors in the register block 26, the addresses of all free processors that can perform the requested function are recorded. The information recorded in this way from the output of the register block 26 is fed to the second control input of the switch 23, the first control input of which receives the code of the requested function. When combining software analysis, taking into account the signals supplied to its inputs, the switch 23 provides the address of the processor that is most appropriate to use in the current situation. As the switch 23, a hard logic combinational circuit can be used that performs the preprogrammed operations and works as follows.

Assume that three processors are connected to this device. The first of them can perform functions 1 and 3 of service, the second all three functions, and the third - functions 2 and 3.

The request for the execution of function 1 comes more often than for the execution of function 2. In this connection, the logic of operation of the logic device according to the algorithms summarized in Table 1 is preliminarily developed.

As can be seen from Table 1, when requesting a service to perform function 3, the device will connect · processor 3 to service, since

function 2 comes less frequently than function 1 and, as a result, the formation of a queue is eliminated, which would arise if function 3 were to be executed by processor 1 rather than 2.

The given example shows the need for a logical analysis of the choice of a serviced processor. With

10 the growth of the number of service functions and the number of processors the logical algorithm of functioning is more obvious and acceptable than the consistent hard selection of a service processor that does not take into account the functions performed by the processor.

The first control input of the switch 23 is served the address of the requested function. The addresses of free processors are fed to the second control input. From the output is given the address of the selected processor.

The addresses of free processors come from block 26 of registers to 25 encoder 28-30, the outputs of which appear logical signals. Through the elements 34-36, 39, they enter the inputs of the decoder 40. It performs the basic function of selecting a process in accordance with the logic of the operation of the device. Possible logical signals at its inputs and outputs are given in table 2, which is compiled on the basis of table 1.

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Elements 34-36 and allow the passage of signals from the decoders 2830 when requesting service functions 1 and 3. And element 39 permits

40 passing the signal from the output of the decoder 28 when requesting service of functions 2 and 3, Elements 37 and 38 eliminate the ambiguity of the choice with function 2 and 3 in lines 7,8,13,

45 16 table 2. The signals for selecting the address of the processors arrive at the inputs of nodes 41-43 of the elements I. The address of one processor or another arrives at the node 44 elements OR from one of the information inputs 21.

At the end of the polling cycle, the transfer signal is fed to the input of the block 24 elements And, the Address from the output of block 24 is fed to the information inputs

55 of the decoder, and the logical signal that appeared at that moment on the element OR 25, selects the decoder 6, at the output of which a load signal appears corresponding to 7

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processor. The signal from the output 18 of the decoder 6 is reset to the corresponding discharge register 4. On the back edge of the signal at the output of the element OR 25 on the driver 11 produces a signal on which the request code and the tracking signal from the input 5 are written to the cell of the memory block 1 at the address from the output of the counter 5 20,

If the subscriber does not issue a request, then the zero code from input 20 is entered into the addressable cell of memory 1. At a signal 17, the subscriber, after enough time to enter information into the memory, removes the request and, if necessary, issues a new one. The signal from the output of the imaging unit 11 transmitted through the delay element 12 (the delay is determined by the recording time in memory block 1) increases by 1 the contents of the counter 5. When a signal arrives at the clock input of the counter 5, a pulse signal at the output of the OR 15 element is already absent and it reads from memory block I. The signal from the output of the delay element 13 (the delay is equal to the time of reading information from memory 1 at a new address from the output of counter 5) the code from the output of memory 1 into register 3 occurs.

As a result, a request is stored in register 3 stored at the address of memory block 1 determined by the enlarged contents of counter 5 (or a null code if the request is not recorded at this address)

In addition, the signal from the% output of the delay element 12 through the element OR 27 is the reset of the memory registers of block 26.

If during the full cycle of counter 9 operation (from its resetting to forming a transfer signal), a free processor capable of performing the requested function is not found, by the transfer signal of counter 9, the contents of counter 5 are increased by ”1" and the request stored in register 3 is written to memory block 3 at the new address from the counter 5. In the cell at the old address, the “redistributed” request is saved, and the request is not entered in the queue (memory block 1) at this address and the signal at the device output 17 is not generated. At the inputs 20, the old, not queued, request. After a search by the counter 5 of all the cells of memory 1, the attempt to distribute "unallocated" on the previous request cycle is repeated,

Claims (1)

Claim A device for assigning tasks to processors, containing two memory blocks, two counters, a clock pulse generator, two registers, a multiplexer, a decoder, a pulse shaper, two delay elements, two OR elements, an AND element, the input of the device request code connected to the first information input of the first the memory block, the second information input, the write input, the address input and the output of which are connected respectively to the input of the device request sign, the output of the first OR element, the output of the first counter and info The primary input of the first register, the inverse output of the lower digit of which is connected to the first input of the element I and the gate input of the multiplexer, the output of which is connected to the read input of the second memory block, the first and second address inputs of which are connected, respectively, to the outputs of the high bits of the first register and information inputs of the second counter, the counting input of which is connected to the output of the clock pulse generator, the output of the decoder is the output of the device and is connected to the zero input of the second register, The input and output of which are connected. ^ respectively, with the busy input of the device’s processors and the multiplexer information input, whose address input is connected to the information output of the second counter, the overflow output of which is connected to the first input of the second OR element and the second input of the AND element whose output is connected with the first input of the first OR element, the output of which is the output of the device request confirmation, the output of the pulse shaper is connected to the second inputs of the first and second OR elements, the input and the output of the first element of the delay is connected, respectively 1488800 Go Respectively, with the output of the second element AND and the counting input of the counter, combined with the input of the second delay element, the output of which is connected to the recording input of the first register, the reset input of which is connected to the device reset input, the high-order outputs of the first register devices that differ in the fact that, in order to expand the field of application of the device due to the choice of processor taking into account the amount of operations performed by it, 15 a block of registers, a switch, a block of elements. AND, the third and fourth elements OR, the device reset input is connected to the first input of the third element OR, the second input and output. 20 which are connected respectively with the output of the first delay element and the reset input of the register block, the output of which is connected to the first control input of the switch, the output of which is connected to the first input of the AND block, the output of which is connected to the information input of the decoder and the input of the OR element, the output of which is connected to the gate "decoder input and the input of the pulse shaper, the information output of the second counter is connected to the address and information inputs of the register block, whose recording input is connected to the output of the second memory block, the second directs input switch coupled to an output significant bits of the first register, a second input of block elements and is connected to the overflow output of the second counter. Table 1 Line Function service Processors free | busy selected one one 1,2,3 one 2 one G, 2 3 one 3 one 1,3 2 one four one 2.3 one 2 five one 3 2.3 one 6 3 2 1,3 2 7 2 1,2,3 - 2 eight 2 2.3 one 2 9 2 1,3 2 3 ten 2 1.2 * 3 2 eleven 2 2 1,3 2 12 2 3 1.2 3 13 3 1,2,3 - 3 14 3 1.2, 3 one 15 3 1,3 2 3 sixteen 3 2.3 one 3 17 3 one 2.3 one 18 3 2 1,3 2 nineteen 3 3 1.2 3 AND 1488800 12 Table 2 Line Decoder 40 inputs Decoder Outputs 40 one 2EEEEE 8 | 9 | ten 63 · 64 65 66 67 68 one one one one 2 3 four five 6 7 eight 9 10 1 1 12 13 14 15 sixteen 17 18 19