SU1756880A1 - Comparator of binary numbers - Google Patents

Abstract

The invention relates to computing and automation and can be used in information processing devices. The aim of the invention is to reduce hardware costs. The device contains comparing units 1 and a group of elements OR 2. Each comparing unit contains elements AND 3. Compared parallel codes are fed to inputs 4 and 5. The result of the comparison is formed at outputs 7. 1 and 1 table.

Description

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The invention relates to computing and automation and can be used in information processing devices.

A device for comparing numbers is known, which contains an OR-NOT element, an ORIG-NE input element, and n analysis nodes (an n-base of a position code number system), each of which includes AND, OR, NOT elements.

The disadvantage of the device is that it only works with positional codes and does not work with binary codes.

The closest in technical essence to the present invention is a device for comparing binary numbers 2, containing n bit comparison nodes, where n is the number of bits of the numbers being compared, two groups of AND-NOT elements, each bit comparison node containing three elements AND NOT, the i-input of the first comparative number of the device, where I 1,2, ..., p, is connected to the first inputs of the first and second elements of the NAND of the 1st bit comparison node, the I-input of the second comparative number of the device is connected to the second input of the first and the first input The third AND-NO elements of the 1st bit comparison node, in each bit-comparison comparison node, the output of the first AND – NE element is connected to the second inputs of the second and third AND – NO elements, the outputs of the second and third AND – NE elements of the 1st bit Comparison node, where

I 1,2p-1, connected to the first inputs

1 I-NOT elements of the first and second groups, the first inputs of the I-NOT elements of the first and second groups are made inverse, the outputs of the second and third elements of the N-NI of the nth comparison node are connected to the second inputs of all AND-NES elements, respectively the second and first groups, mounting OR buses, which are the outputs of the device, the outputs of the second and third AND – HE elements j-ro of the bit comparison node Q n-1, ..., 2,1) are connected to (n + 2- j) -MH inputs Kx elements AND-NOT, respectively, the second and first groups, where K

1.2J-1.

The disadvantage of this device is Quine's complexity for n 8, equal to 118.

The aim of the invention is to reduce hardware costs.

The goal is achieved by the fact that a device for comparing binary numbers, containing n bitwise comparison nodes, where n is the number of digits of the numbers being compared, each bitwise comparison node containing three elements I. The 1st input of the first compared

device numbers where i 1.2p is connected

with the first inputs of the first and second elements AND i-ro of the bitwise comparison node. The 1st input of the second compared number of the device is connected to the second input of the first and the first input of the third element AND the 1st bit comparison node, in each bit comparison node the inverse output of the first element I is connected to the second

0 the inputs of the second and third elements AND, the inverse outputs of the second and third elements AND the n-th bit comparison node are the outputs of the device, the group of elements OR is introduced, and the inverse

5 outputs of the second elements AND of all bit comparison nodes are combined by mounting OR, inverse outputs of the third elements AND of all bit comparison nodes are combined by mounting OR,

0 direct outputs of the second and third elements AND K-ro of a bitwise comparison node, where

K - 1.2p-1, connected respectively to

the first and second inputs of the K-th element OR group, the inverse output of which is co5 through the mounting OR circuits with the inverse output of the first AND (C – H) th bit comparison node, the direct output of the 1st OR element, where I 1,2p-2, connected to the third input

0 (1 + 1) -th element OR group,

The drawing shows a functional diagram of the proposed device.

The device contains comparison units 1i ... n, a group of elements OR

5 2i ... ni, each parallel comparison node 1 i ... n comparison consists of AND 31 ... 3 elements, inputs 4i ... n and 51 .. n, INSTALLING OR 61 and 62 and outputs 7i and 72. Inputs 4i. n and 5i ... n are connected through the elements of And 32 and 3h,

0 INSTALLATION OR 6i and 62 to outputs 7i and 2. The inputs of elements 3 are connected to inputs 4i ... n and 5i ... n, the outputs to inputs of elements AND 32 and 33. The direct outputs of which are connected to the inputs of the corresponding elements

5 OR 2i ... n-i groups, the inverse outputs of which through the INSTALLATION OR are connected to the inverse outputs of the elements AND 3 The direct output of the element OR 2i through the elements OR 22 ... n-2 is connected to the input of the element

0 OR 2ts-1 groups

The device works as follows

With the equality of the numbers at inputs 4 and 5 (Aa B 1), all digits of nodes 1

5 comparisons are formed at the inverse outputs of the AND 32 and I C3 elements of the signal levels of logical 1, which pass to the outputs 7i and 72. At the same time, at the direct outputs of the OR 2 elements, the levels are logical O, and at the inverse ones, the levels of logical 1.

If any digit of the number A, for example, supplied to the input 42, is less than or greater than the same bit of the number B, fed to the input 52, then the inverse outputs of the elements And 32 are level 1 or O, and Z3 is the level Oh or 1 node 12

The result of the comparison in the higher order of the numbers A and B (inputs 4i and 5i) with respect to the rest of the younger categories is predominant with the inequality of the numbers. If there is an inequality in the higher order of the numbers A and B, the inverse output of the element AND 32 or I of the comparison node 1i appears the level of logical O, which is fed to the input 1g or 7i. In this case, the signal of logical 1 direct output of the element AND 32 or Z3 passes through the elements OR 2i ... n-i. At the inverse outputs of the IL-And 2i ... n-i elements, logical O levels are formed, which are fed to the inputs of the AND 32 and I of the neighboring lower comparison nodes 1 and block the comparison of these low-order bits of the numbers being compared.

The state of the elements of the device when comparing different codes A and B is shown in the table.

Therefore, at outputs 7i and 2, when A B is code 11, when A B is code 10 and when A B is code 01. Thus, the proposed device retains the functions of the known and contains less equipment.

Claims (1)

Invention Formula A device for comparing binary numbers, containing n bitwise comparison nodes, where n is the number of digits of the IHHH divisible numbers, each bitwise comparison node containing three 11 elements, the 1st input of the first compared numbers set roevstva, where I 1,2p, is connected to the first the inputs of the first and second elements AND But of the bit comparison node, the 1st input of the second compared number of the device is connected to the second input of the first and the first input of the third elements AND 1 of the second comparison node, in each bit comparison node the inverse output of the first element And connected to the second inputs of the second and third elements AND, the inverse outputs of the second and third elements AND the n-th bit comparison node are the outputs of the device, characterized in that. that, in order to reduce hardware costs, a group of OR elements was introduced into it, the inverse outputs of the second elements AND of all bit units of the comparison are combined by mounting OR, the inverse outputs of the third elements AND of all bit sizes of the comparison are combined by mounting OR, and the third element of the IK-th bit of the comparison node, where K is 1,2n-1, are connected respectively to the first and second inputs of the K-th element of the OR group, the inverse output of which is connected via mounting circuits OR to the inverse output of the first th element and (R + 1) -ro node bit-wise comparison, a direct output of the 1st of the OR group, where 1,2p-2, is connected to the third input of the (1 + 1) th element of the OR group.